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leon, grspw_pkt: support CCSDS/ISO16 data CRC

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When the CCSDS/CCITT CRC-16 and 16-bit ISO-checksum logic is available in
GRSPW2, the DCRCT field is used to determine how to generate the CRC/checksum
code. grspw_hw_sup has been extended with the field ccsds_crc
This commit is contained in:
Martin Aberg
2018-02-21 19:23:35 +01:00
committed by Daniel Hellstrom
parent 1a2656cd8e
commit c2011b474e
2 changed files with 17 additions and 2 deletions
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16
bsps/sparc/include/bsp/grspw_pkt.h
View File

@@ -35,10 +35,20 @@ extern int grspw_work_task_priority;
#define TXPKT_FLAG_HCRC 0x0100
/* Enable Data CRC generation (if CRC is available in HW)
* Data CRC will be appended (one byte at end of packet)
* Data CRC will be appended (one or two byte at end of packet, depending on
* Data CRC type)
*/
#define TXPKT_FLAG_DCRC 0x0200
/* Data CRC type */
#define TXPKT_FLAG_DCRCT_MASK 0x0c00
/* RMAP CRC. 1 byte */
#define TXPKT_FLAG_DCRCT_RMAP 0x0000
/* CCSDS/CCITT CRC-16. 2 byte */
#define TXPKT_FLAG_DCRCT_CCSDS 0x0400
/* 16-bit ISO-checksum (J.G. Fletcher, ISO 8473-1:1998). 2 byte */
#define TXPKT_FLAG_DCRCT_ISO16 0x0800
/* Control how many bytes the beginning of the Header
* the CRC should not be calculated for */
#define TXPKT_FLAG_NOCRC_MASK 0x0000000f
@@ -60,7 +70,8 @@ extern int grspw_work_task_priority;
#define TXPKT_FLAG_NOCRC_LENf 0x0000000f
#define TXPKT_FLAG_INPUT_MASK (TXPKT_FLAG_NOCRC_MASK | TXPKT_FLAG_IE | \
TXPKT_FLAG_HCRC | TXPKT_FLAG_DCRC)
TXPKT_FLAG_HCRC | TXPKT_FLAG_DCRC | \
TXPKT_FLAG_DCRCT_MASK)
/* Marks if packet was transmitted or not */
#define TXPKT_FLAG_TX 0x4000
@@ -176,6 +187,7 @@ struct grspw_hw_sup {
char irq; /* SpW Distributed Interrupt available if 1 */
char irq_num; /* Number of interrupts that can be generated */
char itmr_width; /* SpW Intr. ISR timers bit width. 0=no timer */
char ccsds_crc; /* CCSDS CRC-16 and 16-bit ISO is available */
};
struct grspw_core_stats {

3
bsps/sparc/shared/spw/grspw_pkt.c
View File

@@ -113,6 +113,7 @@ struct grspw_regs {
#define GRSPW_CTRL_RC_BIT 29
#define GRSPW_CTRL_NCH_BIT 27
#define GRSPW_CTRL_PO_BIT 26
#define GRSPW_CTRL_CC_BIT 25
#define GRSPW_CTRL_ID_BIT 24
#define GRSPW_CTRL_LE_BIT 22
#define GRSPW_CTRL_PS_BIT 21
@@ -137,6 +138,7 @@ struct grspw_regs {
#define GRSPW_CTRL_RC (1<<GRSPW_CTRL_RC_BIT)
#define GRSPW_CTRL_NCH (0x3<<GRSPW_CTRL_NCH_BIT)
#define GRSPW_CTRL_PO (1<<GRSPW_CTRL_PO_BIT)
#define GRSPW_CTRL_CC (1<<GRSPW_CTRL_CC_BIT)
#define GRSPW_CTRL_ID (1<<GRSPW_CTRL_ID_BIT)
#define GRSPW_CTRL_LE (1<<GRSPW_CTRL_LE_BIT)
#define GRSPW_CTRL_PS (1<<GRSPW_CTRL_PS_BIT)
@@ -3120,6 +3122,7 @@ static int grspw2_init3(struct drvmgr_dev *dev)
ctrl = REG_READ(&priv->regs->ctrl);
priv->hwsup.rmap = (ctrl & GRSPW_CTRL_RA) >> GRSPW_CTRL_RA_BIT;
priv->hwsup.rmap_crc = (ctrl & GRSPW_CTRL_RC) >> GRSPW_CTRL_RC_BIT;
priv->hwsup.ccsds_crc = (ctrl & GRSPW_CTRL_CC) >> GRSPW_CTRL_CC_BIT;
priv->hwsup.rx_unalign = (ctrl & GRSPW_CTRL_RX) >> GRSPW_CTRL_RX_BIT;
priv->hwsup.nports = 1 + ((ctrl & GRSPW_CTRL_PO) >> GRSPW_CTRL_PO_BIT);
priv->hwsup.ndma_chans = 1 + ((ctrl & GRSPW_CTRL_NCH) >> GRSPW_CTRL_NCH_BIT);