2008-09-19 Joel Sherrill <joel.sherrill@oarcorp.com>

* Makefile.am: Split out various BSPs bspstart.c contents. Move cache
	management code here.
	* mcf5223x/cache/cachepd.c, mcf5235/cache/cachepd.c: New files.

c/src/lib/libcpu/m68k/ChangeLog

@@ -1,3 +1,9 @@
+2008-09-19	Joel Sherrill <joel.sherrill@oarcorp.com>
+
+	* Makefile.am: Split out various BSPs bspstart.c contents. Move cache
+	management code here.
+	* mcf5223x/cache/cachepd.c, mcf5235/cache/cachepd.c: New files.
+
 2008-09-18	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* mcf5206/timer/timerisr.S: Remove unnecessary include of bsp.h

c/src/lib/libcpu/m68k/Makefile.am

@@ -97,12 +97,24 @@ if mcf5223x
 ## mcf5223x/include
 include_mcf5223xdir = $(includedir)/mcf5223x
 include_mcf5223x_HEADERS = mcf5223x/include/mcf5223x.h
+
+## mcf5223x/cache
+noinst_PROGRAMS += mcf5223x/cachepd.rel
+mcf5223x_cachepd_rel_SOURCES = mcf5223x/cache/cachepd.c
+mcf5223x_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS)
+mcf5223x_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 endif
 
 if mcf5235
 ## mcf5235/include
 include_mcf5235dir = $(includedir)/mcf5235
 include_mcf5235_HEADERS = mcf5235/include/mcf5235.h
+
+## mcf5235/cache
+noinst_PROGRAMS += mcf5235/cachepd.rel
+mcf5235_cachepd_rel_SOURCES = mcf5235/cache/cachepd.c
+mcf5235_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS)
+mcf5235_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 endif
 
 if mcf532x

c/src/lib/libcpu/m68k/mcf5223x/cache/cachepd.c

@@ -0,0 +1,37 @@
+/*
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <mcf5223x/mcf5223x.h>
+
+/*
+ * Cannot be frozen
+ */
+void _CPU_cache_freeze_data(void) {}
+void _CPU_cache_unfreeze_data(void) {}
+void _CPU_cache_freeze_instruction(void) {}
+void _CPU_cache_unfreeze_instruction(void) {}
+
+/*
+ * Write-through data cache -- flushes are unnecessary
+ */
+void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+void _CPU_cache_flush_entire_data(void) {}
+
+void _CPU_cache_enable_instruction(void) {}
+void _CPU_cache_disable_instruction(void) {}
+void _CPU_cache_invalidate_entire_instruction(void) {}
+void _CPU_cache_invalidate_1_instruction_line(const void *addr) {}
+
+void _CPU_cache_enable_data(void) {}
+void _CPU_cache_disable_data(void) {}
+void _CPU_cache_invalidate_entire_data(void) {}
+void _CPU_cache_invalidate_1_data_line(const void *addr) {}

c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c

@@ -0,0 +1,101 @@
+/*
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.rtems.com/license/LICENSE.
+ * 
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <mcf5235/mcf5235.h>
+ 
+/*
+ *  Default value for the cacr is set by the BSP
+ */
+extern uint32_t cacr_mode;
+
+/*
+ * Cannot be frozen
+ */
+void _CPU_cache_freeze_data(void) {}
+void _CPU_cache_unfreeze_data(void) {}
+void _CPU_cache_freeze_instruction(void) {}
+void _CPU_cache_unfreeze_instruction(void) {}
+
+/*
+ * Write-through data cache -- flushes are unnecessary
+ */
+void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+void _CPU_cache_flush_entire_data(void) {}
+
+void _CPU_cache_enable_instruction(void)
+{
+    rtems_interrupt_level level;
+
+    rtems_interrupt_disable(level);
+    cacr_mode &= ~MCF5XXX_CACR_DIDI;
+    m68k_set_cacr(cacr_mode);
+    rtems_interrupt_enable(level);
+}
+
+void _CPU_cache_disable_instruction(void)
+{
+    rtems_interrupt_level level;
+
+    rtems_interrupt_disable(level);
+    cacr_mode |= MCF5XXX_CACR_DIDI;
+    m68k_set_cacr(cacr_mode);
+    rtems_interrupt_enable(level);
+}
+
+void _CPU_cache_invalidate_entire_instruction(void)
+{
+    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
+}
+
+void _CPU_cache_invalidate_1_instruction_line(const void *addr)
+{
+    /*
+     * Top half of cache is I-space
+     */
+    addr = (void *)((int)addr | 0x400);
+    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
+}
+
+void _CPU_cache_enable_data(void)
+{
+    rtems_interrupt_level level;
+
+    rtems_interrupt_disable(level);
+    cacr_mode &= ~MCF5XXX_CACR_DISD;
+    m68k_set_cacr(cacr_mode);
+    rtems_interrupt_enable(level);
+}
+
+void _CPU_cache_disable_data(void)
+{
+    rtems_interrupt_level level;
+
+    rtems_interrupt_disable(level);
+    cacr_mode |= MCF5XXX_CACR_DISD;
+    m68k_set_cacr(cacr_mode);
+    rtems_interrupt_enable(level);
+}
+
+void _CPU_cache_invalidate_entire_data(void)
+{
+    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
+}
+
+void _CPU_cache_invalidate_1_data_line(const void *addr)
+{
+    /*
+     * Bottom half of cache is D-space
+     */
+    addr = (void *)((int)addr & ~0x400);
+    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
+}