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BSP submitted by Thomas Doerfler <td@imd.m.isar.de>:

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Finally I am through: I have found the last bugs that made RTEMS-
    4.0-beta3 start on my ppc403 board from ROM. So now the '403
    support is up to date again.

    Roughly I have added the following features:
        - support for the on-chip interrupt controller (in a separate module)
        - interrupt support for the console device
        - termios support for the console device

    ==============================================
    Since the BSP behaivour changed in some details (console no
    longer is polling, other memory layout etc) I have created a new
    BSP "helas403" rather than changing the "papyrus" BSP. The old
    "polled" console driver still sticks around in "console.c.polled"
    To get the BSP up and running, I had to create the new BSP files
    (derived from papyrus). Besides that, the following source areas
    have been changed:

    - c/src/lib/libcpu/powerpc/ppc403: changes to console driver, small
    changes to clock driver, new "ictrl" interrupt controller driver

    - c/src/exec/score/cpu/powerpc/ppc.h: some small changes
    (added ppc403 characteristics like a exception vector prefix
    register, some special register definitions). I am quite sure, they
    are compatible with the existing sources, although I did not check

    - c/src/exec/score/cpu/powerpc/cpu.c: There is one severe
    limitation in the exception entries: Due to the current code
    arrangement, the "branch absolute" to the ISR handler may only
    jump to the first 128MByte or the last 128MByte of the 4GByte
    address range. When the ppc403 is running out of ROM, the ROM
    functions are located in the last 128MByte (0xFFF00000 and up).
    These addresses were not handled correctly (sign reduced) in
    "install_raw_handler". The change I added should work on existing
    ppc BSPs aswell...

    - c/src/lib/libc/termios.c: During my tests, I added one change you
    sent me, so this patch will already be incorporated in the current
    source tree.

    There are some smaller changes, see the attached diff file.

    =========================================
    Concerning the GNU toolchain:

    I tried several tool chains. Finally I almost succeeded with

    egcs-1.0.3a with patch  egcs-1.0.3-rtems-diff-19980527

    I had to add the following lines to the egcs files. Without them
    configure complaint that the cross compiler could not generate
    executable output.
    - additional lines needed in egcs distribution in file
      gcc/config/rs6000/rtems.h:

    +++ lines start
    #undef STARTFILE_DEFAULT_SPEC
    #define STARTFILE_DEFAULT_SPEC "ecrti.o%s"

    #undef  ENDFILE_DEFAULT_SPEC
    #define ENDFILE_DEFAULT_SPEC "ecrtn.o%s"
    ++++ lines end

    As far as I have seen in the Changelog of egcs, you have recently
    sent two patches affecting the powerpc support, but they were
    added in the wrong order.... :-(

    egcs-19980628 with patch egcs-19980628-rtems-diff-19980707 does
    not work!

    I used binutils 2.9.1 with patch binutils-2.9.1-rtems-diff-19980515
     (binutils 2.8.1 does not work, internal error in gas)
    and newlib-1.8.0 with patch newlib-1.8.0-rtems-diff-19980707

    Finally I had to poke a line in the "bit" script, since, on my LINUX
    machine, the GNU make is only available as "make", not as
    "gmake"...

    For all the tools and newlib I selected configuration "powerpc-
    rtems".

--------------------------------------------
IMD Ingenieurbuero fuer Microcomputertechnik
Thomas Doerfler           Herbststrasse 8
D-82178 Puchheim          Germany
email:    td@imd.m.isar.de
This commit is contained in:
Joel Sherrill
1998-09-30 21:50:42 +00:00
parent 05d499280c
commit be4284d0f2
20 changed files with 2201 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
c/src/lib/libbsp/powerpc/helas403/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SRCS=README
all: $(SRCS)
# wrapup is the one that actually builds and installs the library
# from the individual .rel files built in other directories
SUB_DIRS=include dlentry flashentry startup wrapup

48
c/src/lib/libbsp/powerpc/helas403/README Normal file
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#
# $Id$
#
BSP NAME: helas403
BOARD: IMD, helas-ppc
BUS: N/A
CPU FAMILY: ppc
CPU: PowerPC 403GA
COPROCESSORS: N/A
MODE: 32 bit mode
DEBUG MONITOR: Modified Motorola FBUG
PERIPHERALS
===========
TIMERS: 403GA internal
RESOLUTION: .04 microseconds
SERIAL PORTS: 403GA internal
REAL-TIME CLOCK: 403GA internal
DMA: 403GA internal
VIDEO: none
SCSI: none
NETWORKING: none
DRIVER INFORMATION
==================
CLOCK DRIVER: 403GA internal
IOSUPP DRIVER: N/A
SHMSUPP: N/A
TIMER DRIVER: 403GA internal
TTY DRIVER: 403GA internal
STDIO
=====
PORT: Console port 0
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
Notes
=====
helas403 only supports single processor operations.

23
c/src/lib/libbsp/powerpc/helas403/bsp_specs Normal file
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%rename cpp old_cpp
%rename lib old_lib
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
*cpp:
%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded)
*lib:
%{!qrtems: %(old_lib)} %{qrtems: ecrti%O%s --start-group \
%{!qrtems_debug: -lrtemsall} %{qrtems_debug: -lrtemsall_g} \
-lc -lgcc --end-group \
%{!qnolinkcmds: -T linkcmds%s}}
*startfile:
%{!qrtems: %(old_startfile)} %{qrtems: \
%{!qrtems_debug: } \
%{qrtems_debug: }}
*link:
%{!qrtems: %(old_link)} %{qrtems: -dc -dp -u __vectors -u flash_entry -N }

23
c/src/lib/libbsp/powerpc/helas403/bsp_specs.dl Normal file
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%rename cpp old_cpp
%rename lib old_lib
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
*cpp:
%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded)
*lib:
%{!qrtems: %(old_lib)} %{qrtems: ecrti%O%s --start-group \
%{!qrtems_debug: -lrtemsall} %{qrtems_debug: -lrtemsall_g} \
-lc -lgcc --end-group \
%{!qnolinkcmds: -T linkcmds%s}}
*startfile:
%{!qrtems: %(old_startfile)} %{qrtems: \
%{!qrtems_debug: } \
%{qrtems_debug: }}
*link:
%{!qrtems: %(old_link)} %{qrtems: -dc -dp -u __vectors -u download_entry -N }

59
c/src/lib/libbsp/powerpc/helas403/dlentry/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
PGM=${ARCH}/dlentry.rel
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES=
# Assembly source names, if any, go here -- minus the .s
S_PIECES=dlentry
S_FILES=$(S_PIECES:%=%.s)
S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o)
SRCS=$(C_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
${PGM}: ${SRCS} ${OBJS}
$(make-rel)
all: ${ARCH} $(SRCS) $(PGM)
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
install: all

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c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.s Normal file
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/* dlentry.s
*
* This file contains the entry code for RTEMS programs starting
* after download to RAM
*
* Author: Thomas Doerfler <td@imd.m.isar.de>
* IMD Ingenieurbuero fuer Microcomputertechnik
*
* COPYRIGHT (c) 1998 by IMD
*
* Changes from IMD are covered by the original distributions terms.
* This file has been derived from the papyrus BSP:
*
* This file contains the entry veneer for RTEMS programs
* downloaded to Papyrus.
*
* Author: Andrew Bray <andy@i-cubed.co.uk>
*
* COPYRIGHT (c) 1995 by i-cubed ltd.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of i-cubed limited not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* i-cubed limited makes no representations about the suitability
* of this software for any purpose.
*
* $Id$
*/
#include "asm.h"
/*
* The helas403 ELF link scripts support three special sections:
* .entry The actual entry point
* .vectors The section containing the interrupt entry veneers.
*/
/*
* Downloaded code loads the vectors separately to 0x00000100,
* so .entry can be over 256 bytes.
*
* The other sections are linked in the following order:
* .entry
* .text
* .data
* .bss
* see linker command file for section placement
*
* The initial stack is set to stack.end
*
* All the entry veneer has to do is to clear the BSS.
*/
/*
* GDB likes to have debugging information for the entry veneer.
* Here was some DWARF information. IMD removed it, because we
* could not check, whether it was still correct. Sorry.
*/
#if PPC_ASM == PPC_ASM_ELF
.section .entry
#else
.csect .text[PR]
#endif
PUBLIC_VAR (download_entry)
SYM(download_entry):
bl .startup
base_addr:
/*---------------------------------------------------------------------------
* Parameters from linker
*--------------------------------------------------------------------------*/
toc_pointer:
#if PPC_ASM == PPC_ASM_ELF
.long s.got
#else
.long TOC[tc0]
#endif
bss_length:
.long bss.size
bss_addr:
.long bss.start
stack_top:
.long stack.end
/*---------------------------------------------------------------------------
* Reset_entry.
*--------------------------------------------------------------------------*/
.startup:
/* Get start address, stack grows down from here... */
mflr r1
/* Assume Bank regs set up..., cache etc. */
bl bssclr
.extern SYM(__vectors)
lis r2,__vectors@h /* set EVPR exc. vector prefix */
mtspr evpr,r2
/*-------------------------------------------------------------------
* C_setup.
*------------------------------------------------------------------*/
lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */
lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */
addi r1,r1,-56-4 /* start stack at text_addr - 56 */
addi r3,r0,0x0 /* clear r3 */
stw r3, 0(r1) /* Clear stack chain */
stw r3, 4(r1)
stw r3, 8(r1)
stw r3, 12(r1)
.extern SYM (boot_card)
b SYM (boot_card) /* call the first C routine */
/*---------------------------------------------------------------------------
* bssclr.
*--------------------------------------------------------------------------*/
bssclr:
/*-------------------------------------------------------------------
* Data move finished, zero out bss.
*------------------------------------------------------------------*/
lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */
lwz r3,bss_length-base_addr(r1) /* bss length */
rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */
beqlr /* no bss */
mtctr r3 /* set ctr reg */
xor r6,r6,r6 /* r6 = 0 */
clear_bss:
stswi r6,r2,0x4 /* store r6 */
addi r2,r2,0x4 /* update r2 */
bdnz clear_bss /* decrement counter and loop */
blr /* return */
.L_text_e:
#if PPC_ABI == PPC_ABI_POWEROPEN
DESCRIPTOR (startup)
#endif

59
c/src/lib/libbsp/powerpc/helas403/flashentry/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
PGM=${ARCH}/flashentry.rel
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES=
# Assembly source names, if any, go here -- minus the .s
S_PIECES=flashentry
S_FILES=$(S_PIECES:%=%.s)
S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o)
SRCS=$(C_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
${PGM}: ${SRCS} ${OBJS}
$(make-rel)
all: ${ARCH} $(SRCS) $(PGM)
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
install: all

469
c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.s Normal file
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/* flashentry.s
*
* This file contains the entry code for RTEMS programs starting
* directly from Flash.
*
* Author: Thomas Doerfler <td@imd.m.isar.de>
* IMD Ingenieurbuero fuer Microcomputertechnik
*
* COPYRIGHT (c) 1998 by IMD
*
* Changes from IMD are covered by the original distributions terms.
* This file has been derived from the papyrus BSP:
*
* This file contains the entry veneer for RTEMS programs
* stored in Papyrus' flash ROM.
*
* Author: Andrew Bray <andy@i-cubed.co.uk>
*
* COPYRIGHT (c) 1995 by i-cubed ltd.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of i-cubed limited not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* i-cubed limited makes no representations about the suitability
* of this software for any purpose.
*
* $Id$
*/
#include "asm.h"
#include <rtems/score/ppc.h>
/*----------------------------------------------------------------------------
* Reset_entry.
*---------------------------------------------------------------------------*/
#if PPC_ASM == PPC_ASM_ELF
.section .reset,"ax",@progbits
/* this section MUST be located at absolute address 0xFFFFFFFC
or last word of EPROM */
#else
.csect .text[PR]
#endif
ba flash_entry /* this is the first instruction after reset */
.previous
/*----------------------------------------------------------------------------
* ROM Vector area.
*---------------------------------------------------------------------------*/
#if PPC_ASM == PPC_ASM_ELF
.section .entry,"ax",@progbits
#else
.csect .text[PR]
#endif
PUBLIC_VAR (flash_entry)
SYM (flash_entry):
bl .startup /* call startup, link reg points to base_addr */
base_addr:
/*----------------------------------------------------------------------------
* Parameters from linker
*---------------------------------------------------------------------------*/
toc_pointer:
#if PPC_ASM == PPC_ASM_ELF
.long s.got
#else
.long TOC[tc0]
#endif
text_length:
.long text.size
text_addr:
.long text.start
copy_src:
.long copy.src
copy_length:
.long copy.size
copy_dest:
.long copy.dest
bss_length:
.long bss.size
bss_addr:
.long bss.start
stack_top:
.long stack.end
/*----------------------------------------------------------------------------
* from Reset_entry.
*---------------------------------------------------------------------------*/
.startup:
/* Get start address, r1 points to label base_addr */
mflr r1
/* Set up Bank regs, cache etc. */
/* set up bank register BR0 for Flash-EPROM:
* NOTE: bank size should stay 1MByte, this is standard size
* after RESET
* base addr = Fffxxxxx -> 0b11111111........................
* bank size = 1 MByte -> 0b........000..................... (std)
* bank use = readonly -> 0b...........01...................
* seq. fill = targ frst-> 0b.............0..................
* burst mode= enable -> 0b..............1.................
* bus width = 8 bit -> 0b...............00...............
* ready pin = disable -> 0b.................0..............
* first wait= 2 clocks -> 0b..................0010..........
* burst wait= 2 clocks -> 0b......................10........
* CSon time = 0 clocks -> 0b........................0.......
* OEon time = 0 clocks -> 0b.........................0......
* WBon time = 1 clocks -> 0b..........................1.....
* WBoff time= 0 clocks -> 0b...........................0....
* Hold time = 1 clocks -> 0b............................001.
* ram type = SRAM(ign)-> 0b...............................1
* value 0b11111111000010100000101000100011
* 0x F F 0 A 0 A 2 3
*/
lis r2,0xFF0A
ori r2,r2,0x0A23
mtdcr br0,r2 /* write to DCR BR0 */
/*--------------------------------------------------------------------
* test various RAM configurations (from big to small per bank)
*------------------------------------------------------------------*/
/*--------------------------------------------------------------------
* test RAM config 16 MByte (1x4Mx32Bit)
*------------------------------------------------------------------*/
/* set up bank register BR7 for DRAM:
* base addr = 000xxxxx -> 0b00000000........................
* bank size = 16MByte -> 0b........100.....................
* bank use = readwrite-> 0b...........11...................
* seq. fill = targ.frst-> 0b.............0..................
* early RAS = disabled -> 0b..............0.................
* bus width = 32bit -> 0b...............10...............
* adr mux = internal -> 0b.................0..............
* RAS to CAS= 2 clocks -> 0b..................1.............
* Alt. Rfrsh= normal -> 0b...................0............
* page mode = enabled -> 0b....................1...........
* first wait= 1 clocks -> 0b.....................01.........
* burst wait= 1 clocks -> 0b.......................01.......
* precharge = 1 clocks -> 0b.........................0......
* RAS Rfrsh = 2 clocks -> 0b..........................1.....
* Rfrsh Itvl= 512 clks -> 0b...........................1000.
* ram type = DRAM -> 0b...............................0
* value 0b00000000100110010010101010110000
* 0x 0 0 9 9 2 A B 0
*/
lis r2,0x0099
ori r2,r2,0x2AB0
mtdcr br7,r2 /* write to DCR BR7*/
lis r2,0x0000 /* start address = 0x00000000 */
lis r3,0x0100 /* size 16 MB = 0x01000000 */
bl ramacc /* test memory accessibility */
cmpi 0,0,r4,0 /* memory ok? else test smaller size */
bne ramcfgt18
/*--------------------------------------------------------------------
* test RAM config 32 MByte (2x4Mx32Bit)
*------------------------------------------------------------------*/
/* set up bank register BR7 like above
* set up bank register BR6 for DRAM:
* base addr = 010xxxxx -> 0b00010000........................
* bank size = 16MByte -> 0b........100..................... (for now)
* bank use = readwrite-> 0b...........11...................
* seq. fill = targ.frst-> 0b.............0..................
* early RAS = disabled -> 0b..............0.................
* bus width = 32bit -> 0b...............10...............
* adr mux = internal -> 0b.................0..............
* RAS to CAS= 2 clocks -> 0b..................1.............
* Alt. Rfrsh= normal -> 0b...................0............
* page mode = enabled -> 0b....................1...........
* first wait= 1 clocks -> 0b.....................01.........
* burst wait= 1 clocks -> 0b.......................01.......
* precharge = 1 clocks -> 0b.........................0......
* RAS Rfrsh = 2 clocks -> 0b..........................1.....
* Rfrsh Itvl= 512 clks -> 0b...........................1000.
* ram type = DRAM -> 0b...............................0
* value 0b00010000100110010010101010110000
* 0x 1 0 9 9 2 A B 0
*/
lis r2,0x1099
ori r2,r2,0x2AB0
mtdcr br6,r2 /* write to DCR BR6*/
lis r2,0x0100 /* start address = 0x01000000 */
lis r3,0x0100 /* size 16 MB = 0x01000000 */
bl ramacc /* test memory accessibility */
cmpi 0,0,r4,0 /* memory ok? else test smaller size */
beq ramcfgok /* ok, we found configuration... +/
lis r2,0x0000 /* disable BR6, config not ok */
mtdcr br6,r2 /* write to DCR BR6*/
b ramcfgok /* and finish configuration */
ramcfgt18:
/*--------------------------------------------------------------------
* test RAM config 8 MByte (1x2Mx32Bit)
*------------------------------------------------------------------*/
/* set up bank register BR7 for DRAM:
* base addr = 000xxxxx -> 0b00000000........................
* bank size = 8MByte -> 0b........011.....................
* bank use = readwrite-> 0b...........11...................
* seq. fill = targ.frst-> 0b.............0..................
* early RAS = disabled -> 0b..............0.................
* bus width = 32bit -> 0b...............10...............
* adr mux = internal -> 0b.................0..............
* RAS to CAS= 2 clocks -> 0b..................1.............
* Alt. Rfrsh= normal -> 0b...................0............
* page mode = enabled -> 0b....................1...........
* first wait= 1 clocks -> 0b.....................01.........
* burst wait= 1 clocks -> 0b.......................01.......
* precharge = 1 clocks -> 0b.........................0......
* RAS Rfrsh = 2 clocks -> 0b..........................1.....
* Rfrsh Itvl= 512 clks -> 0b...........................1000.
* ram type = DRAM -> 0b...............................0
* value 0b00000000011110010010101010110000
* 0x 0 0 7 9 2 A B 0
*/
lis r2,0x0079
ori r2,r2,0x2AB0
mtdcr br7,r2 /* write to DCR BR7 */
lis r2,0x0000 /* start address = 0x00000000 */
lis r3,0x0080 /* size 8 MB = 0x00800000 */
bl ramacc /* test memory accessibility */
cmpi 0,0,r4,0 /* memory ok? else test smaller size */
bne ramcfgt14
/*--------------------------------------------------------------------
* test RAM config 16 MByte (2x2Mx32Bit)
*------------------------------------------------------------------*/
/* set up bank register BR7 like above
* set up bank register BR6 for DRAM:
* base addr = 008xxxxx -> 0b00001000........................
* bank size = 08MByte -> 0b........011..................... (for now)
* bank use = readwrite-> 0b...........11...................
* seq. fill = targ.frst-> 0b.............0..................
* early RAS = disabled -> 0b..............0.................
* bus width = 32bit -> 0b...............10...............
* adr mux = internal -> 0b.................0..............
* RAS to CAS= 2 clocks -> 0b..................1.............
* Alt. Rfrsh= normal -> 0b...................0............
* page mode = enabled -> 0b....................1...........
* first wait= 1 clocks -> 0b.....................01.........
* burst wait= 1 clocks -> 0b.......................01.......
* precharge = 1 clocks -> 0b.........................0......
* RAS Rfrsh = 2 clocks -> 0b..........................1.....
* Rfrsh Itvl= 512 clks -> 0b...........................1000.
* ram type = DRAM -> 0b...............................0
* value 0b00001000011110010010101010110000
* 0x 0 8 7 9 2 A B 0
*/
lis r2,0x0879
ori r2,r2,0x2AB0
mtdcr br6,r2 /* write to DCR BR6*/
lis r2,0x0080 /* start address = 0x00800000 */
lis r3,0x0080 /* size 8 MB = 0x00800000 */
bl ramacc /* test memory accessibility */
cmpi 0,0,r4,0 /* memory ok? else test smaller size */
beq ramcfgok /* ok, we found configuration... +/
lis r2,0x0000 /* disable BR6, config not ok */
mtdcr br6,r2 /* write to DCR BR6*/
b ramcfgok /* and finish configuration */
ramcfgt14:
/*--------------------------------------------------------------------
* test RAM config 4 MByte (1x1Mx32Bit)
*------------------------------------------------------------------*/
/* set up bank register BR7 for DRAM:
* base addr = 000xxxxx -> 0b00000000........................
* bank size = 4MByte -> 0b........010.....................
* bank use = readwrite-> 0b...........11...................
* seq. fill = targ.frst-> 0b.............0..................
* early RAS = disabled -> 0b..............0.................
* bus width = 32bit -> 0b...............10...............
* adr mux = internal -> 0b.................0..............
* RAS to CAS= 2 clocks -> 0b..................1.............
* Alt. Rfrsh= normal -> 0b...................0............
* page mode = enabled -> 0b....................1...........
* first wait= 1 clocks -> 0b.....................01.........
* burst wait= 1 clocks -> 0b.......................01.......
* precharge = 1 clocks -> 0b.........................0......
* RAS Rfrsh = 2 clocks -> 0b..........................1.....
* Rfrsh Itvl= 512 clks -> 0b...........................1000.
* ram type = DRAM -> 0b...............................0
* value 0b00000000010110010010101010110000
* 0x 0 0 5 9 2 A B 0
*/
/*
* FIXME: this is the minimum size supported, should test and
* report error, when failed
*/
lis r2,0x0059
ori r2,r2,0x2AB0
mtdcr br7,r2 /* write to DCR BR7*/
/*--------------------------------------------------------------------
* test RAM config 8 MByte (2x1Mx32Bit)
*------------------------------------------------------------------*/
/* set up bank register BR7 like above
* set up bank register BR6 for DRAM:
* base addr = 004xxxxx -> 0b00000100........................
* bank size = 4MByte -> 0b........010..................... (for now)
* bank use = readwrite-> 0b...........11...................
* seq. fill = targ.frst-> 0b.............0..................
* early RAS = disabled -> 0b..............0.................
* bus width = 32bit -> 0b...............10...............
* adr mux = internal -> 0b.................0..............
* RAS to CAS= 2 clocks -> 0b..................1.............
* Alt. Rfrsh= normal -> 0b...................0............
* page mode = enabled -> 0b....................1...........
* first wait= 1 clocks -> 0b.....................01.........
* burst wait= 1 clocks -> 0b.......................01.......
* precharge = 1 clocks -> 0b.........................0......
* RAS Rfrsh = 2 clocks -> 0b..........................1.....
* Rfrsh Itvl= 512 clks -> 0b...........................1000.
* ram type = DRAM -> 0b...............................0
* value 0b00000100010110010010101010110000
* 0x 0 4 5 9 2 A B 0
*/
lis r2,0x0459
ori r2,r2,0x2AB0
mtdcr br6,r2 /* write to DCR BR6*/
lis r2,0x0040 /* start address = 0x00400000 */
lis r3,0x0040 /* size 4 MB = 0x00400000 */
bl ramacc /* test memory accessibility */
cmpi 0,0,r4,0 /* memory ok? else test smaller size */
beq ramcfgok /* ok, we found configuration... +/
lis r2,0x0000 /* disable BR6, config not ok */
mtdcr br6,r2 /* write to DCR BR6*/
b ramcfgok /* and finish configuration */
ramcfgok:
/*--------------------------------------------------------------------
* init the DRAM where STACK+ DATA+ BBS will be placed. If this is OK
* we will return here.
*-------------------------------------------------------------------*/
bl rom2ram
/* clear caches */
addi r2,0,PPC_I_CACHE/PPC_CACHE_ALIGNMENT
mtctr r2 /* count the loops needed... */
xor r2,r2,r2 /* start at adr zero */
icinvlp:
iccci 0,r2
addi r2,r2,PPC_CACHE_ALIGNMENT
bdnz icinvlp
addi r2,r0,PPC_D_CACHE/PPC_CACHE_ALIGNMENT
mtctr r2 /* count the loops needed... */
xor r2,r2,r2 /* start at adr 0 */
dcinvlp:
dccci 0,r2
addi r2,r2,PPC_CACHE_ALIGNMENT
bdnz dcinvlp
/*--------------------------------------------------------------------
* Enable two 128MB cachable regions.
* FEPROM is cachable at 0xFFF00000..0xFFFFFFFF
* DRAM is cachable at 0x00000000..0x00FFFFFF
* FEPROM is noncachable at 0x7FF00000..0x7FFFFFFF
* DRAM is noncachable at 0x80000000..0x80FFFFFF
*-------------------------------------------------------------------*/
addis r2,r0,0x8000
addi r2,r2,0x0001
mtspr iccr, r2 /* ICCR */
mtspr dccr, r2 /* DCCR */
.extern SYM(__vectors)
lis r2,__vectors@h /* set EVPR exc. vector prefix */
mtspr evpr,r2
lis r2,0x0000
ori r2,r2,0x0000
mtmsr r2 /* set default msr */
lis r2,0x0000 /* do not allow critical IRQ */
ori r2,r2,0x0000
mtdcr exier, r2 /* disable all external IRQs */
addi r2,r0,-1 /* r2 = 0xffffffff */
mtdcr exisr, r2 /* clear all pendingdisable IRQs */
/*--------------------------------------------------------------------
* C_setup.
*-------------------------------------------------------------------*/
lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */
lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */
addi r1,r1,-56 /* start stack at data_addr - 56 */
addi r3,r0,0x0 /* clear r3 */
stw r3, 0(r1) /* Clear stack chain */
stw r3, 4(r1)
stw r3, 8(r1)
stw r3, 12(r1)
.extern SYM (boot_card)
b SYM (boot_card) /* call the first C routine */
/*----------------------------------------------------------------------------
* Rom2ram.
*---------------------------------------------------------------------------*/
rom2ram:
lwz r2,copy_dest-base_addr(r1) /* start of data set by loader */
lwz r3,copy_length-base_addr(r1) /* data length */
rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */
mtctr r3 /* set ctr reg */
/*--------------------------------------------------------------------
* Calculate offset of data in image.
*-------------------------------------------------------------------*/
lwz r4,copy_src-base_addr(r1) /* get start of copy area */
move_data:
lswi r6,r4,0x4 /* load r6 */
stswi r6,r2,0x4 /* store r6 */
addi r4,r4,0x4 /* update r4 */
addi r2,r2,0x4 /* update r2 */
bdnz move_data /* decrement counter and loop */
/*--------------------------------------------------------------------
* Data move finished, zero out bss.
*-------------------------------------------------------------------*/
lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */
lwz r3,bss_length-base_addr(r1) /* bss length */
rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */
beqlr /* no bss */
mtctr r3 /* set ctr reg */
xor r6,r6,r6 /* r6 = 0 */
clear_bss:
stswi r6,r2,0x4 /* store r6 */
addi r2,r2,0x4 /* update r2 */
bdnz clear_bss /* decrement counter and loop */
blr /* return */
/*----------------------------------------------------------------------------
* ramacc test accessibility of RAM
* input: r2 = start address, r3 = length (in byte)
* output: r4 = 0 -> ok, !=0 -> fail
*---------------------------------------------------------------------------*/
ramacc:
xor r4,r4,r4 /* r4 = 0 */
stw r4,0(r2) /* init ram at start address */
addi r4,r0,0x04 /* set start shift */
ramaccf1:
cmp 0,0,r4,r3 /* compare with length */
bge ramaccfx /* r4 >= r3? then finished */
add r5,r4,r2 /* get next address to fill */
stw r4,0(r5) /* store new pattern */
add r4,r4,r4 /* r4 = r4*2 */
b ramaccf1 /* and then next loop */
ramaccfx:
lwz r4,0(r2) /* get memory at start adr */
blr
#if PPC_ABI == PPC_ABI_POWEROPEN
DESCRIPTOR (startup)
#endif

35
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
H_FILES = $(srcdir)/bsp.h $(srcdir)/coverhd.h
#
# Equate files are for including from assembly preprocessed by
# gm4 or gasp. No examples are provided except for those for
# other CPUs. The best way to generate them would be to
# provide a program which generates the constants used based
# on the C equivalents.
#
EQ_FILES =
SRCS=$(H_FILES) $(EQ_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: $(SRCS)
$(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE)
$(INSTALL) -m 444 $(EQ_FILES) $(PROJECT_INCLUDE)
install: all

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/* bsp.h
*
* This include file contains all HELAS-403 board IO definitions.
*
* Author: Thomas Doerfler <td@imd.m.isar.de>
* IMD Ingenieurbuero fuer Microcomputertechnik
*
* COPYRIGHT (c) 1998 by IMD
*
* Changes from IMD are covered by the original distributions terms.
* This file has been derived from the papyrus BSP.
*
* Author: Andrew Bray <andy@i-cubed.co.uk>
*
* COPYRIGHT (c) 1995 by i-cubed ltd.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of i-cubed limited not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* i-cubed limited makes no representations about the suitability
* of this software for any purpose.
*
* Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __HELAS403_h
#define __HELAS403_h
#ifdef __cplusplus
extern "C" {
#endif
#ifdef ASM
/* Definition of where to store registers in alignment handler */
#define ALIGN_REGS 0x0140
#else
#include <rtems.h>
#include <console.h>
#include <clockdrv.h>
#include <console.h>
#include <iosupp.h>
/*
* Define the time limits for RTEMS Test Suite test durations.
* Long test and short test duration limits are provided. These
* values are in seconds and need to be converted to ticks for the
* application.
*
*/
#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */
#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */
/*
* Stuff for Time Test 27
*/
#define MUST_WAIT_FOR_INTERRUPT 0
#define Install_tm27_vector( handler ) set_vector( (handler), PPC_IRQ_SCALL, 1 )
#define Cause_tm27_intr() asm volatile ("sc")
#define Clear_tm27_intr()
#define Lower_tm27_intr()
/* Constants */
#define RAM_START 0
#define RAM_END 0x00800000
/* miscellaneous stuff assumed to exist */
extern rtems_configuration_table BSP_Configuration; /* owned by BSP */
extern rtems_cpu_table Cpu_table; /* owned by BSP */
/*
* Device Driver Table Entries
*/
/*
* NOTE: Use the standard Console driver entry
*/
/*
* NOTE: Use the standard Clock driver entry
*/
/* functions */
rtems_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
);
#endif /* ASM */
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

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/* coverhd.h
*
* This include file has defines to represent the overhead associated
* with calling a particular directive from C. These are used in the
* Timing Test Suite to ignore the overhead required to pass arguments
* to directives. On some CPUs and/or target boards, this overhead
* is significant and makes it difficult to distinguish internal
* RTEMS execution time from that used to call the directive.
* This file should be updated after running the C overhead timing
* test. Once this update has been performed, the RTEMS Time Test
* Suite should be rebuilt to account for these overhead times in the
* timing results.
*
* NOTE: If these are all zero, then the times reported include
* all calling overhead including passing of arguments.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
/*
* Updated for a 25MHz Papyrus by Andrew Bray <andy@i-cubed.co.uk>
*
* Units are 100ns.
*
* These numbers are of questionable use, as they are developed by calling
* the routine many times, thus getting its entry veneer into the (small)
* cache on the 403GA. This in general is not true of the RTEMS timing
* tests, which usually call a routine only once, thus having no cache loaded
* advantage.
*
* Whether the directive times are useful after deducting the function call
* overhead is also questionable. The user is more interested generally
* in the total cost of a directive, not the cost if the procedure call
* is inlined! (In general this is not true).
*
* Andrew Bray 18/08/1995
*
*/
#ifndef __COVERHD_h
#define __COVERHD_h
#ifdef __cplusplus
extern "C" {
#endif
#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 1
#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1
#define CALLING_OVERHEAD_TASK_CREATE 3
#define CALLING_OVERHEAD_TASK_IDENT 1
#define CALLING_OVERHEAD_TASK_START 1
#define CALLING_OVERHEAD_TASK_RESTART 1
#define CALLING_OVERHEAD_TASK_DELETE 1
#define CALLING_OVERHEAD_TASK_SUSPEND 1
#define CALLING_OVERHEAD_TASK_RESUME 1
#define CALLING_OVERHEAD_TASK_SET_PRIORITY 1
#define CALLING_OVERHEAD_TASK_MODE 1
#define CALLING_OVERHEAD_TASK_GET_NOTE 1
#define CALLING_OVERHEAD_TASK_SET_NOTE 1
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 4
#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1
#define CALLING_OVERHEAD_INTERRUPT_CATCH 1
#define CALLING_OVERHEAD_CLOCK_GET 4
#define CALLING_OVERHEAD_CLOCK_SET 3
#define CALLING_OVERHEAD_CLOCK_TICK 1
#define CALLING_OVERHEAD_TIMER_CREATE 1
#define CALLING_OVERHEAD_TIMER_IDENT 1
#define CALLING_OVERHEAD_TIMER_DELETE 1
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 2
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 5
#define CALLING_OVERHEAD_TIMER_RESET 1
#define CALLING_OVERHEAD_TIMER_CANCEL 1
#define CALLING_OVERHEAD_SEMAPHORE_CREATE 2
#define CALLING_OVERHEAD_SEMAPHORE_IDENT 1
#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1
#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 1
#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1
#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 2
#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 1
#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1
#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 1
#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 1
#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 1
#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 2
#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 1
#define CALLING_OVERHEAD_EVENT_SEND 1
#define CALLING_OVERHEAD_EVENT_RECEIVE 2
#define CALLING_OVERHEAD_SIGNAL_CATCH 1
#define CALLING_OVERHEAD_SIGNAL_SEND 1
#define CALLING_OVERHEAD_PARTITION_CREATE 3
#define CALLING_OVERHEAD_PARTITION_IDENT 1
#define CALLING_OVERHEAD_PARTITION_DELETE 1
#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 1
#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 1
#define CALLING_OVERHEAD_REGION_CREATE 3
#define CALLING_OVERHEAD_REGION_IDENT 1
#define CALLING_OVERHEAD_REGION_DELETE 1
#define CALLING_OVERHEAD_REGION_GET_SEGMENT 2
#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 1
#define CALLING_OVERHEAD_PORT_CREATE 2
#define CALLING_OVERHEAD_PORT_IDENT 1
#define CALLING_OVERHEAD_PORT_DELETE 1
#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 1
#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2
#define CALLING_OVERHEAD_IO_INITIALIZE 2
#define CALLING_OVERHEAD_IO_OPEN 2
#define CALLING_OVERHEAD_IO_CLOSE 2
#define CALLING_OVERHEAD_IO_READ 2
#define CALLING_OVERHEAD_IO_WRITE 2
#define CALLING_OVERHEAD_IO_CONTROL 2
#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1
#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 1
#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 1
#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1
#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 1
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

56
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@:@srcdir@/../../../shared
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
PGM=${ARCH}/startup.rel
# C source names, if any, go here -- minus the .c
C_PIECES=bspclean bsplibc bsppost bspstart main sbrk setvec
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES=
SRCS=$(C_FILES) $(H_FILES)
OBJS=$(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
${PGM}: ${SRCS} ${OBJS}
$(make-rel)
all: ${ARCH} $(SRCS) $(PGM)
$(INSTALL) $(srcdir)/linkcmds ${PROJECT_RELEASE}/lib
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
install: all

44
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/* bsp_cleanup()
*
* This routine normally is part of start.s and usually returns
* control to a monitor.
*
* INPUT: NONE
*
* OUTPUT: NONE
*
* Author: Andrew Bray <andy@i-cubed.co.uk>
*
* COPYRIGHT (c) 1995 by i-cubed ltd.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of i-cubed limited not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* i-cubed limited makes no representations about the suitability
* of this software for any purpose.
*
* Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/bspclean.c:
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
void bsp_cleanup( void )
{
rtems_fatal_error_occurred(0);
}

201
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/* bsp_start()
*
* This routine starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before this routine is invoked.
*
* INPUT: NONE
*
* OUTPUT: NONE
*
* Author: Thomas Doerfler <td@imd.m.isar.de>
* IMD Ingenieurbuero fuer Microcomputertechnik
*
* COPYRIGHT (c) 1998 by IMD
*
* Changes from IMD are covered by the original distributions terms.
* This file has been derived from the papyrus BSP:
*
* Author: Andrew Bray <andy@i-cubed.co.uk>
*
* COPYRIGHT (c) 1995 by i-cubed ltd.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of i-cubed limited not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* i-cubed limited makes no representations about the suitability
* of this software for any purpose.
*
* Modifications for spooling console driver and control of memory layout
* with linker command file by
* Thomas Doerfler <td@imd.m.isar.de>
* for these modifications:
* COPYRIGHT (c) 1997 by IMD, Puchheim, Germany.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies. IMD makes no representations about the suitability
* of this software for any purpose.
*
* Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/bspstart.c:
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
* On-Line Applications Research Corporation (OAR).
* All rights assigned to U.S. Government, 1994.
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
* $Id$
*/
#include <bsp.h>
#include <ictrl.h>
#include <rtems/libio.h>
#include <libcsupport.h>
#include <string.h>
#include <fcntl.h>
#ifdef STACK_CHECKER_ON
#include <stackchk.h>
#endif
/*
* The original table from the application and our copy of it with
* some changes.
*/
extern rtems_configuration_table Configuration;
rtems_configuration_table BSP_Configuration;
rtems_cpu_table Cpu_table;
char *rtems_progname;
void *bsp_ram_end = (void *)RAM_END; /* first addr behind avail. ram area */
/* Initialize whatever libc we are using
* called from postdriver hook
*/
void bsp_postdriver_hook(void);
void bsp_libc_init( void *, unsigned32, int );
/*
*
* bsp_predriver_hook
*
* Before drivers are setup.
*/
void bsp_predriver_hook(void)
{
rtems_status_code status;
/* init the PPC403GA external interrupt controller handler... */
status = ictrl_init();
}
/*
* Function: bsp_pretasking_hook
* Created: 95/03/10
*
* Description:
* BSP pretasking hook. Called just before drivers are initialized.
* Used to setup libc and install any BSP extensions.
*
* NOTES:
* Must not use libc (to do io) from here, since drivers are
* not yet initialized.
*
*/
void bsp_pretasking_hook(void)
{
extern int _end;
rtems_unsigned32 heap_start;
heap_start = (rtems_unsigned32) &_end;
if (heap_start & (CPU_ALIGNMENT-1))
heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
bsp_libc_init((void *) heap_start, 64 * 1024, 0);
#ifdef RTEMS_DEBUG
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
#endif
}
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
/*
* Allocate the memory for the RTEMS Work Space. This can come from
* a variety of places: hard coded address, malloc'ed from outside
* RTEMS world (e.g. simulator or primitive memory manager), or (as
* typically done by stock BSPs) by subtracting the required amount
* of work space from the last physical address on the CPU board.
*/
/*
* Need to "allocate" the memory for the RTEMS Workspace and
* tell the RTEMS configuration where it is. This memory is
* not malloc'ed. It is just "pulled from the air".
*/
/* FIXME: this should be modified. work_space_size cannot be valid
* now, since console_reserve_resources will modify something...
*/
/* FIME: plan usage of RAM better:
- make top of ram dynamic,
- take out some part for persistant log
- make rest of ram to heap...
-remove RAM_END from bsp.h, this cannot be valid...
or must be a function call
*/
BSP_Configuration.work_space_start = (void *)
((char *)(bsp_ram_end)) - BSP_Configuration.work_space_size;
/*
* Account for the console's resources
*/
console_reserve_resources( &BSP_Configuration );
/*
* initialize the CPU table for this BSP
*/
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.predriver_hook = bsp_predriver_hook;
Cpu_table.postdriver_hook = bsp_postdriver_hook;
Cpu_table.interrupt_stack_size = 4 * 1024;
Cpu_table.clicks_per_usec = 25;
Cpu_table.serial_per_sec = 25000000;
Cpu_table.serial_external_clock = 0;
Cpu_table.timer_internal_clock = 1;
Cpu_table.serial_xon_xoff = 0;
Cpu_table.serial_cts_rts = 1;
Cpu_table.serial_rate = 9600;
Cpu_table.timer_average_overhead = 2;
Cpu_table.timer_least_valid = 3;
Cpu_table.exceptions_in_RAM = TRUE;
}

200
c/src/lib/libbsp/powerpc/helas403/startup/linkcmds Normal file
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/*
* This file contains directives for the GNU linker which are specific
* to the helas-403
* This file is intended to be used together with flashentry.s
* it will generate a ROM that can be started directly after powerup reset
* $Id$
*/
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
"elf32-powerpc")
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/usr/local/powerpc-rtems/lib);
ENTRY(flash_entry)
MEMORY
{
RAM : ORIGIN = 0, LENGTH = 8M
FLASH : ORIGIN = 0xFFF00000, LENGTH = 512K
}
/* DIRTY TRICK: repeat addresses here, so we can work with them... */
flash.start = 0xFFF00000;
flash.size = 512K;
SECTIONS
{
.entry :
{
*(.entry)
} > FLASH /* this is ROM for flash_entry */
.text :
{
text.start = . ;
*(.entry2)
*(.text)
*(.rodata)
*(.rodata1)
*(.descriptors)
*(rom_ver)
etext = ALIGN(0x10);
_etext = .;
__CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
*(.ctors)
LONG(0)
__CTOR_END__ = .;
__DTOR_LIST__ = .;
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
*(.dtors)
LONG(0)
__DTOR_END__ = .;
*(.lit)
*(.shdata)
*(.init)
*(.fini)
. = ALIGN(0x10);
_endtext = .;
text.end = .;
copy.src = .;
copy.tmptop.txt = .;
} > FLASH /* this is ROM for flash_entry */
text.size = text.end - text.start;
/* R/W Data */
/* place vectors to start at offset 0x100... */
/* IMPORTANT: sections ".fill" and ".vectors" must be the first in RAM!!*/
.fill 0x00010000 :
{
. = . + 0x0100;
} > RAM
.vectors : AT (copy.src)
{
copy.dest = .;
*(.vectors)
. = ALIGN(0x10);
copy.tmptop.vec = .;
} > RAM
.data : AT (copy.tmptop.vec - copy.dest + copy.src)
{
*(.data)
*(.data1)
PROVIDE (__SDATA_START__ = .);
*(.sdata)
. = ALIGN(0x10);
copy.tmptop.dat = .;
} > RAM
PROVIDE (__EXCEPT_START__ = .);
.gcc_except_table : AT (copy.tmptop.dat - copy.dest + copy.src)
{
*(.gcc_except_table)
. = ALIGN(0x10);
copy.tmptop.exc = .;
} >RAM
PROVIDE (__EXCEPT_END__ = .);
__GOT_START__ = .;
.got : AT (copy.tmptop.exc - copy.dest + copy.src)
{
s.got = .;
*(.got.plt) *(.got)
. = ALIGN(0x10);
copy.tmptop.got = .;
} > RAM
__GOT_END__ = .;
.got1 : AT (copy.tmptop.got - copy.dest + copy.src)
{
*(.got1)
. = ALIGN(0x10);
copy.tmptop.gt1 = .;
} >RAM
PROVIDE (__GOT2_START__ = .);
PROVIDE (_GOT2_START_ = .);
.got2 : AT (copy.tmptop.gt1 - copy.dest + copy.src)
{
*(.got2)
. = ALIGN(0x10);
copy.tmptop.gt2 = .;
} >RAM
PROVIDE (__GOT2_END__ = .);
PROVIDE (_GOT2_END_ = .);
PROVIDE (__FIXUP_START__ = .);
PROVIDE (_FIXUP_START_ = .);
.fixup : AT (copy.tmptop.gt2 - copy.dest + copy.src)
{
*(.fixup)
. = ALIGN(0x10);
copy.tmptop.fix = .;
} >RAM
PROVIDE (_FIXUP_END_ = .);
PROVIDE (__FIXUP_END__ = .);
PROVIDE (__SDATA2_START__ = .);
.sdata2 : AT (copy.tmptop.fix - copy.dest + copy.src)
{
*(.sdata2)
. = ALIGN(0x10);
copy.tmptop.sda = .;
} >RAM
copy.size = copy.tmptop.sda - copy.dest;
.sbss2 :
{
*(.sbss2)
} >RAM
PROVIDE (__SBSS2_END__ = .);
__SBSS_START__ = .;
.bss :
{
bss.start = .;
*(.bss) *(.sbss) *(COMMON)
bss.end = ALIGN(4);
} > RAM
__SBSS_END__ = .;
bss.size = bss.end - bss.start;
/* reserve 16KByte for stack... */
stack.end = bss.end + 16K;
PROVIDE(_end = stack.end);
.line 0 : { *(.line) }
.debug 0 : { *(.debug) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_aregion 0 : { *(.debug_aregion) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
/*
* place reset instruction into last word of FLASH
* NOTE: after reset, PPC403 starts executing from address
* 0xFFFFFFFC
* The reset section is placed in ROM at 0xF7FFFFFC instead,
* but a mirror of this address exists at 0xFFFFFFFC due to
* the initial memory controller setup
*/
.reset flash.start - 4 + flash.size :
{
*(.reset)
} > FLASH
}

142
c/src/lib/libbsp/powerpc/helas403/startup/linkcmds.dl Normal file
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/*
* This file contains directives for the GNU linker which are specific
* to the helas403
* This file is intended to be used together with dlentry.s
* it will generate downloadable code
*
* $Id$
*/
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
"elf32-powerpc")
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/usr/local/powerpc-rtems/lib);
ENTRY(download_entry)
MEMORY
{
RAM : ORIGIN = 0, LENGTH = 8M
FLASH : ORIGIN = 0xFFF00000, LENGTH = 512K
}
SECTIONS
{
.vectors : 0x00010100
{
*(.vectors)
} > RAM
.text :
{
text.start = . ;
*(.entry)
*(.entry2)
*(.text)
*(.rodata)
*(.rodata1)
*(.descriptors)
*(rom_ver)
etext = ALIGN(0x10);
_etext = .;
__CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
*(.ctors)
LONG(0)
__CTOR_END__ = .;
__DTOR_LIST__ = .;
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
*(.dtors)
LONG(0)
__DTOR_END__ = .;
*(.lit)
*(.shdata)
*(.init)
*(.fini)
_endtext = ALIGN(0x10);
text.end = .;
} > RAM
text.size = text.end - text.start;
/* R/W Data */
.data :
{
*(.data)
*(.data1)
PROVIDE (__SDATA_START__ = .);
*(.sdata)
} > RAM
PROVIDE (__EXCEPT_START__ = .);
.gcc_except_table :
{
*(.gcc_except_table)
} >RAM
PROVIDE (__EXCEPT_END__ = .);
__GOT_START__ = .;
.got :
{
s.got = .;
*(.got.plt) *(.got)
} > RAM
__GOT_END__ = .;
.got1 :
{
*(.got1)
} >RAM
PROVIDE (__GOT2_START__ = .);
PROVIDE (_GOT2_START_ = .);
.got2 :
{
*(.got2)
} >RAM
PROVIDE (__GOT2_END__ = .);
PROVIDE (_GOT2_END_ = .);
PROVIDE (__FIXUP_START__ = .);
PROVIDE (_FIXUP_START_ = .);
.fixup : { *(.fixup) } >RAM
PROVIDE (_FIXUP_END_ = .);
PROVIDE (__FIXUP_END__ = .);
PROVIDE (__SDATA2_START__ = .);
.sdata2 : { *(.sdata2) } >RAM
.sbss2 : { *(.sbss2) } >RAM
PROVIDE (__SBSS2_END__ = .);
.sbss2 : { *(.sbss2) } >RAM
PROVIDE (__SBSS2_END__ = .);
__SBSS_START__ = .;
.bss :
{
bss.start = .;
*(.bss) *(.sbss) *(COMMON)
bss.end = ALIGN(4);
} > RAM
__SBSS_END__ = .;
bss.size = bss.end - bss.start;
PROVIDE(_end = bss.end);
.line 0 : { *(.line) }
.debug 0 : { *(.debug) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_aregion 0 : { *(.debug_aregion) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
}

58
c/src/lib/libbsp/powerpc/helas403/startup/setvec.c Normal file
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/* set_vector
*
* This routine installs an interrupt vector on the target Board/CPU.
* This routine is allowed to be as board dependent as necessary.
*
* INPUT:
* handler - interrupt handler entry point
* vector - vector number
* type - 0 indicates raw hardware connect
* 1 indicates RTEMS interrupt connect
*
* RETURNS:
* address of previous interrupt handler
*
* Author: Andrew Bray <andy@i-cubed.co.uk>
*
* COPYRIGHT (c) 1995 by i-cubed ltd.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of i-cubed limited not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* i-cubed limited makes no representations about the suitability
* of this software for any purpose.
*
* Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/setvec.c:
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
rtems_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
)
{
rtems_isr_entry previous_isr;
rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
return previous_isr;
}

197
c/src/lib/libbsp/powerpc/helas403/times Normal file
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#
# Timing Test Suite Results for the Papyrus BSP
#
# NOTE: The Papyrus is a proprietary PPC403 based board. But it is the
# only BSP currently available for the PowerPC family.
#
# $Id$
#
NOTE: This BSP is user submitted and no timing information
is currently avaiable.
Board: Papyrus
CPU: IBM 403GA
Clock Speed: 33 Mhz
Memory Configuration: SRAM, DRAM, cache, etc
Wait States:
Times Reported in: cycles, microseconds, etc
Timer Source: Count Down Timer, on-CPU cycle counter, etc
Column A: unused
Column B: unused
# DESCRIPTION A B
== ================================================================= ==== ====
1 rtems_semaphore_create 20
rtems_semaphore_delete 21
rtems_semaphore_obtain: available 15
rtems_semaphore_obtain: not available -- NO_WAIT 15
rtems_semaphore_release: no waiting tasks 16
2 rtems_semaphore_obtain: not available -- caller blocks 62
3 rtems_semaphore_release: task readied -- preempts caller 55
4 rtems_task_restart: blocked task -- preempts caller 77
rtems_task_restart: ready task -- preempts caller 70
rtems_semaphore_release: task readied -- returns to caller 25
rtems_task_create 57
rtems_task_start 31
rtems_task_restart: suspended task -- returns to caller 36
rtems_task_delete: suspended task 47
rtems_task_restart: ready task -- returns to caller 37
rtems_task_restart: blocked task -- returns to caller 46
rtems_task_delete: blocked task 50
5 rtems_task_suspend: calling task 51
rtems_task_resume: task readied -- preempts caller 49
6 rtems_task_restart: calling task 59
rtems_task_suspend: returns to caller 18
rtems_task_resume: task readied -- returns to caller 19
rtems_task_delete: ready task 50
7 rtems_task_restart: suspended task -- preempts caller 70
8 rtems_task_set_priority: obtain current priority 12
rtems_task_set_priority: returns to caller 27
rtems_task_mode: obtain current mode 5
rtems_task_mode: no reschedule 5
rtems_task_mode: reschedule -- returns to caller 8
rtems_task_mode: reschedule -- preempts caller 39
rtems_task_set_note 13
rtems_task_get_note 13
rtems_clock_set 33
rtems_clock_get 3
9 rtems_message_queue_create 110
rtems_message_queue_send: no waiting tasks 37
rtems_message_queue_urgent: no waiting tasks 37
rtems_message_queue_receive: available 31
rtems_message_queue_flush: no messages flushed 12
rtems_message_queue_flush: messages flushed 16
rtems_message_queue_delete 26
10 rtems_message_queue_receive: not available -- NO_WAIT 15
rtems_message_queue_receive: not available -- caller blocks 62
11 rtems_message_queue_send: task readied -- preempts caller 72
12 rtems_message_queue_send: task readied -- returns to caller 39
13 rtems_message_queue_urgent: task readied -- preempts caller 72
14 rtems_message_queue_urgent: task readied -- returns to caller 39
15 rtems_event_receive: obtain current events 1
rtems_event_receive: not available -- NO_WAIT 12
rtems_event_receive: not available -- caller blocks 56
rtems_event_send: no task readied 12
rtems_event_receive: available 12
rtems_event_send: task readied -- returns to caller 24
16 rtems_event_send: task readied -- preempts caller 55
17 rtems_task_set_priority: preempts caller 62
18 rtems_task_delete: calling task 83
19 rtems_signal_catch 9
rtems_signal_send: returns to caller 15
rtems_signal_send: signal to self 18
exit ASR overhead: returns to calling task 22
exit ASR overhead: returns to preempting task 49
20 rtems_partition_create 35
rtems_region_create 23
rtems_partition_get_buffer: available 15
rtems_partition_get_buffer: not available 13
rtems_partition_return_buffer 18
rtems_partition_delete 16
rtems_region_get_segment: available 22
rtems_region_get_segment: not available -- NO_WAIT 21
rtems_region_return_segment: no waiting tasks 19
rtems_region_get_segment: not available -- caller blocks 64
rtems_region_return_segment: task readied -- preempts caller 74
rtems_region_return_segment: task readied -- returns to caller 44
rtems_region_delete 16
rtems_io_initialize 2
rtems_io_open 1
rtems_io_close 1
rtems_io_read 1
rtems_io_write 1
rtems_io_control 1
21 rtems_task_ident 149
rtems_message_queue_ident 145
rtems_semaphore_ident 156
rtems_partition_ident 145
rtems_region_ident 148
rtems_port_ident 145
rtems_timer_ident 145
rtems_rate_monotonic_ident 145
22 rtems_message_queue_broadcast: task readied -- returns to caller 42
rtems_message_queue_broadcast: no waiting tasks 17
rtems_message_queue_broadcast: task readied -- preempts caller 78
23 rtems_timer_create 14
rtems_timer_fire_after: inactive 22
rtems_timer_fire_after: active 24
rtems_timer_cancel: active 15
rtems_timer_cancel: inactive 13
rtems_timer_reset: inactive 21
rtems_timer_reset: active 23
rtems_timer_fire_when: inactive 34
rtems_timer_fire_when: active 34
rtems_timer_delete: active 19
rtems_timer_delete: inactive 17
rtems_task_wake_when 69
24 rtems_task_wake_after: yield -- returns to caller 9
rtems_task_wake_after: yields -- preempts caller 45
25 rtems_clock_tick 4
26 _ISR_Disable 0
_ISR_Flash 1
_ISR_Enable 1
_Thread_Disable_dispatch 0
_Thread_Enable_dispatch 7
_Thread_Set_state 11
_Thread_Disptach (NO FP) 31
context switch: no floating point contexts 21
context switch: self 10
context switch: to another task 10
context switch: restore 1st FP task 25
fp context switch: save idle, restore idle 31
fp context switch: save idle, restore initialized 19
fp context switch: save initialized, restore initialized 20
_Thread_Resume 7
_Thread_Unblock 7
_Thread_Ready 9
_Thread_Get 4
_Semaphore_Get 2
_Thread_Get: invalid id 0
27 interrupt entry overhead: returns to interrupted task 6
interrupt exit overhead: returns to interrupted task 6
interrupt entry overhead: returns to nested interrupt 6
interrupt exit overhead: returns to nested interrupt 5
interrupt entry overhead: returns to preempting task 7
interrupt exit overhead: returns to preempting task 36
28 rtems_port_create 16
rtems_port_external_to_internal 11
rtems_port_internal_to_external 11
rtems_port_delete 16
29 rtems_rate_monotonic_create 15
rtems_rate_monotonic_period: initiate period -- returns to caller 21
rtems_rate_monotonic_period: obtain status 13
rtems_rate_monotonic_cancel 16
rtems_rate_monotonic_delete: inactive 18
rtems_rate_monotonic_delete: active 20
rtems_rate_monotonic_period: conclude periods -- caller blocks 53

56
c/src/lib/libbsp/powerpc/helas403/wrapup/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
BSP_PIECES=startup dlentry flashentry
# pieces to pick up out of libcpu/ppc
CPU_PIECES=ppc403/clock ppc403/timer ppc403/console ppc403/vectors ppc403/ictrl
GENERIC_PIECES=
# bummer; have to use $foreach since % pattern subst rules only replace 1x
OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \
$(foreach piece, $(CPU_PIECES), \
../../../../libcpu/$(RTEMS_CPU)/$(piece)/$(ARCH)/$(notdir $(piece)).rel) \
$(foreach piece, $(GENERIC_PIECES), \
../../../$(piece)/$(ARCH)/$(piece).rel)
LIB=$(ARCH)/libbsp.a
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/lib.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
$(LIB): ${OBJS}
$(make-library)
all: ${ARCH} $(SRCS) $(LIB)
$(INSTALL_VARIANT) -m 644 $(LIB) ${PROJECT_RELEASE}/lib
install: all

110
make/custom/helas403.cfg Normal file
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#
# Config file for a PowerPC 403 based helas403 card
#
# $Id$
#
# this is derived from:
#
# Config file for a PowerPC 403 based papyrus card
#
# Id: papyrus.cfg,v 1.7 1998/06/27 17:09:47 joel Exp
#
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU=powerpc
RTEMS_CPU_MODEL=ppc403
# This is the actual bsp directory used during the build process.
RTEMS_BSP_FAMILY=helas403
# These should be defined in targopt.h now.
#CPU_DEFINES=-DPPC_ABI=PPC_ABI_POWEROPEN \
# -DPPC_ASM=PPC_ASM_ELF -DPPC_VECTOR_FILE_BASE=0x0100
# This target does NOT support the KA9Q TCP/IP stack so ignore requests
# to enable it.
HAS_KA9Q=no
# This section makes the target dependent options file.
# NDEBUG (C library)
# if defined asserts do not generate code. This is commonly used
# as a command line option.
#
# RTEMS_TEST_NO_PAUSE (RTEMS tests)
# do not pause between screens of output in the rtems tests
#
# RTEMS_DEBUG (RTEMS)
# If defined, debug checks in RTEMS and support library code are enabled.
#
#
# PPC_VECTOR_FILE_BASE (PowerPC)
# This defines the base address of the exception table.
# NOTE: Vectors are actually at 0xFFF00000 but file starts at offset 0x0100
#
# PPC_ABI (PowerPC)
# This defines the calling convention (Application Binary Interface)
# used in this configuration. EABI is the only one supported.
# This BSP was initially developed using the PowerOpen ABI.
#
# PPC_ASM (PowerPC)
# This defines the assembly language format used in this configuration.
# ELF is the only one supported.
#
# PPC_USE_SPRG (RTEMS PowerPC port)
# If defined, then the PowerPC specific code in RTEMS will use some
# of the special purpose registers to slightly optimize interrupt
# response time. The use of these registers can conflict with
# other tools like debuggers.
define make-target-options
@echo "/* #define NDEBUG 1 */ " >>$@
@echo "#define RTEMS_TEST_NO_PAUSE 1" >>$@
@echo "/* #define RTEMS_DEBUG 1 */" >>$@
@echo "#define PPC_VECTOR_FILE_BASE 0x0100" >>$@
@echo "#define PPC_ABI PPC_ABI_EABI" >>$@
@echo "#define PPC_ASM PPC_ASM_ELF" >>$@
@echo "#define PPC_USE_SPRG 1" >>$@
endef
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
#
CPU_CFLAGS = -mcpu=403
# optimize flag: typically -0, could use -O4 or -fast
# -O4 is ok for RTEMS
# NOTE: some level of -O may be actually required by inline assembler
CFLAGS_OPTIMIZE_V=-O4 -fno-keep-inline-functions
# No start file
START_BASE=
# The following are definitions of make-exe which will work using ld as
# is currently required. It is expected that as of gcc 2.8, the end user
# will be able to override parts of the compilers specs and link using gcc.
ifeq ($(RTEMS_USE_GCC272),yes)
# The --defsym arguments define arguments which are required by the linkcmds
# file which is designed for gcc 2.8
define make-exe
$(LD) $(XLDFLAGS) -T $(LINKCMDS) \
--defsym __fini=0 --defsym __init=0 \
-o $@ -u atexit -u __vectors -u download_entry \
$(START_FILE) $(LINK_OBJS) --start-group $(LINK_LIBS) --end-group
$(NM) -g -n $@ > $(basename $@).num
$(SIZE) $@
endef
else
define make-exe
$(CC) $(CFLAGS) -o $(basename $@).exe \
$(LINK_OBJS) $(LINK_LIBS)
$(NM) -g -n $@ > $(basename $@).num
$(SIZE) $@
endef
endif
# Miscellaneous additions go here