bsps/arm: Support system level ARM Generic Timer

Update #4202.

bsps/shared/dev/clock/arm-generic-timer.c

@@ -138,11 +138,22 @@ CPU_Counter_ticks _CPU_Counter_read(void)
   return (uint32_t) arm_gt_clock_get_count();
 }
 
+static void arm_gt_system_init(void)
+{
+#ifdef ARM_GENERIC_TIMER_SYSTEM_BASE
+  volatile uint32_t *cntcr;
+
+  cntcr = (volatile uint32_t *) ARM_GENERIC_TIMER_SYSTEM_BASE;
+  *cntcr = ARM_GENERIC_TIMER_SYSTEM_CNTCR;
+#endif
+}
+
 static void arm_gt_clock_early_init(void)
 {
   uint32_t frequency;
-  arm_gt_clock_set_control(0x3);
 
+  arm_gt_system_init();
+  arm_gt_clock_set_control(0x3);
   arm_generic_timer_get_config(
     &frequency,
     &arm_gt_clock_instance.irq

spec/build/bsps/arm/optgtsysbase.yml

@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: 709033984
+default-by-variant:
+- value: 2856517632
+  variants:
+  - arm/fvp_cortex_r52
+description: |
+  Defines the base address of the memory-mapped system level ARM Generic Timer.
+format: '{:#010x}'
+enabled-by: true
+links: []
+name: ARM_GENERIC_TIMER_SYSTEM_BASE
+type: build

spec/build/bsps/arm/optgtsyscntcr.yml

@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: 1
+default-by-variant:
+- value: 257
+  variants:
+  - arm/fvp_cortex_r52
+description: |
+  Defines the initialization value of the CNTCR register of the memory-mapped
+  system level ARM Generic Timer.
+format: '{:#010x}'
+enabled-by: true
+links: []
+name: ARM_GENERIC_TIMER_SYSTEM_CNTCR
+type: build