forked from Imagelibrary/rtems
arm: Fix ARMv7-M exception handler
Store the stack pointer of the exception context to the exception frame. Close #3987.
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@@ -40,13 +40,20 @@ void __attribute__((naked)) _ARMV7M_Exception_default( void )
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"stm sp, {r0-r12}\n"
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"tst lr, #4\n" /* Check if bit 2 of LR is zero. If so, PSR.Z = 1 */
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"itte eq\n" /* IF bit 2 of LR is zero... (PSR.Z == 1) */
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"mrseq r0, msp\n" /* THEN we were using MSP. */
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"addeq r0, %[cpufsz]\n" /* THEN, set r0 = old MSP value. */
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"mrsne r0, psp\n" /* ELSE it's not zero; we were using PSP. */
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"add r2, r0, %[v7mlroff]\n"
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"add r1, sp, %[cpulroff]\n"
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"ldm r2, {r3-r5}\n" /* Grab LR, PC and PSR from the stack.. */
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"stm r1, {r3-r5}\n" /* ..and store them in our CPU_Exception_frame. */
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"mrseq r3, msp\n" /* THEN we were using MSP */
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"addeq r3, %[cpufsz]\n" /* THEN, set r3 = old MSP value */
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"mrsne r3, psp\n" /* ELSE it is not zero; we were using PSP */
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"add r2, r3, %[v7mlroff]\n"
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"add r1, sp, %[cpuspoff]\n"
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"ldm r2, {r4-r6}\n" /* Grab LR, PC and xPSR from the stack */
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"tst lr, #16\n" /* Check if we have an FP state on the frame */
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"ite eq\n"
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"addeq r3, #104\n" /* Back to previous SP with FP state */
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"addne r3, #32\n" /* Back to previous SP without FP state */
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"tst r6, #512\n" /* Check xPSR if the SP was aligned */
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"it ne\n"
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"addne r3, #4\n" /* Undo alignment */
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"stm r1, {r3-r6}\n" /* Store to CPU_Exception_frame */
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"mrs r1, ipsr\n"
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"str r1, [sp, %[cpuvecoff]]\n"
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@@ -85,7 +92,7 @@ void __attribute__((naked)) _ARMV7M_Exception_default( void )
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"b _ARM_Exception_default\n"
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:
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: [cpufsz] "i" (sizeof(CPU_Exception_frame)),
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[cpulroff] "i" (offsetof(CPU_Exception_frame, register_lr)),
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[cpuspoff] "i" (offsetof(CPU_Exception_frame, register_sp)),
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[v7mlroff] "i" (offsetof(ARMV7M_Exception_frame, register_lr)),
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[cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector)),
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[cpuvfpoff] "i" (ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET),
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