forked from Imagelibrary/rtems
Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information are now in libcpu. This required significant rework of the score/cpu header files and the creation of multiple header files and subdirectories in libcpu/i960.
This commit is contained in:
Joel Sherrill
@@ -10,7 +10,7 @@ SUBDIRS = rtems
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C_FILES = cpu.c
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C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
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H_FILES = asm.h i960RP.h
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H_FILES = asm.h
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S_FILES = cpu_asm.S
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S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
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@@ -11,18 +11,6 @@
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*
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* $Id$
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*/
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/*
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* 1999/04/26: added support for Intel i960RP
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*/
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#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
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#elif defined(__i960RP__)
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#elif defined(__i960KA__)
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#else
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#warning "*** ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY ***"
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#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
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#endif
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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@@ -62,45 +50,6 @@ unsigned32 _CPU_ISR_Get_level( void )
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return level;
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}
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/*PAGE
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*
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* _CPU_ISR_install_raw_handler
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*/
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#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
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#define i960_vector_caching_enabled( _prcb ) \
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((_prcb)->control_tbl->icon & 0x2000)
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#elif defined(__i960RP__)
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#define i960_vector_caching_enabled( _prcb ) \
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((*((unsigned int *) ICON_ADDR)) & 0x2000)
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#elif defined(__i960KA__)
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#define i960_vector_caching_enabled( _prcb ) 0
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#endif
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void _CPU_ISR_install_raw_handler(
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unsigned32 vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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i960_PRCB *prcb = _CPU_Table.Prcb;
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proc_ptr *cached_intr_tbl = NULL;
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/* The i80960CA does not support vectors 0-7. The first 9 entries
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* in the Interrupt Table are used to manage pending interrupts.
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* Thus vector 8, the first valid vector number, is actually in
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* slot 9 in the table.
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*/
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*old_handler = prcb->intr_tbl[ vector + 1 ];
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prcb->intr_tbl[ vector + 1 ] = new_handler;
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if ( i960_vector_caching_enabled( prcb ) )
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if ( (vector & 0xf) == 0x2 ) /* cacheable? */
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cached_intr_tbl[ vector >> 4 ] = new_handler;
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}
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/*PAGE
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*
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* _CPU__ISR_install_vector
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@@ -130,60 +79,3 @@ void _CPU_ISR_install_vector(
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_ISR_Vector_table[ vector ] = new_handler;
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}
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/*PAGE
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*
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* _CPU_Install_interrupt_stack
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*/
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#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
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#define soft_reset( prcb ) \
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{ register i960_PRCB *_prcb = (prcb); \
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register unsigned32 *_next=0; \
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register unsigned32 _cmd = 0x30000; \
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asm volatile( "lda next,%1; \
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sysctl %0,%1,%2; \
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next: mov g0,g0" \
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: "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
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: "0" (_cmd), "1" (_next), "2" (_prcb) ); \
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}
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#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
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#define soft_reset( prcb ) \
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{ register i960_PRCB *_prcb = (prcb); \
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register unsigned32 *_next=0; \
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register unsigned32 _cmd = 0x300; \
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asm volatile( "lda next,%1; \
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sysctl %0,%1,%2; \
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next: mov g0,g0" \
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: "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
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: "0" (_cmd), "1" (_next), "2" (_prcb) ); \
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}
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#elif defined(__i960KA__)
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#define soft_reset( prcb )
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#endif
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void _CPU_Install_interrupt_stack( void )
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{
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i960_PRCB *prcb = _CPU_Table.Prcb;
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unsigned32 level;
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#if defined(__i960RP__) || defined(__i960_RP__)
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unsigned32 *isp = (int *) ISP_ADDR;
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#endif
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/*
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* Set the Interrupt Stack in the PRCB and force a reload of it.
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* Interrupts are disabled for safety.
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*/
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_CPU_ISR_Disable( level );
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prcb->intr_stack = _CPU_Interrupt_stack_low;
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#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
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soft_reset( prcb );
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#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
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*isp = (unsigned32) prcb->intr_stack;
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#endif
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_CPU_ISR_Enable( level );
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}
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@@ -1,7 +1,5 @@
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/* cpu_asm.s
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*
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* This file contains all assembly code for the i960CA implementation
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* of RTEMS.
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/*
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* This file contains all assembly code for the i960 port of RTEMS.
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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@@ -13,12 +11,6 @@
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* $Id$
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*/
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.data
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.align 4
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_soft_reset_reg_save:
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.word 0
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.word 0
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.word 0
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.word 0
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_ISR_reg_save:
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.word 0
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.word 0
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@@ -217,30 +209,3 @@ __ISR_Dispatch:
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movq r12,g4
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ret
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#if !defined(__i960KA__)
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/*PAGE
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*
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* void __i960_soft_reset_asm
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*
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* Flush the register cache and save the important (fp, pfp, sp) registers,
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* which are clobbered by the reinit operation. (Not documented, but it happens).
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*/
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.globl __i960_soft_reset_asm
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__i960_soft_reset_asm:
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flushreg # flush register cache
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mov fp, r4
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mov pfp, r5
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mov sp, r6
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stt r4, _soft_reset_reg_save # save fp, pfp, sp
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lda __i960_reset_done, r4
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ldconst 0x300, r5
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sysctl r5, r4, g0 # reinit: clobbers almost all registers
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__i960_reset_done:
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ldt _soft_reset_reg_save, r4 # restore fp, pfp, sp
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mov r4, fp
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mov r5, pfp
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mov r6, sp
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ret
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#endif
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@@ -1,318 +0,0 @@
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/*
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* i960RP Related Definitions.
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*
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* NOTE: There is some commonality with the JX series which is
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* not currently supported by RTEMS.
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*
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* $Id$
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*/
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#ifndef __I960RP_h
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#define __I960RP_h
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/*----------------------------------------------------------*/
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/* Example 6. Include File (evrp.h) */
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/*----------------------------------------------------------*/
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/* Define JX Core memory mapped register addresses */
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/* Common to Jx and RP: */
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#define DLMCON_ADDR 0xff008100
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#define LMAR0_ADDR 0xff008108
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#define LMMR0_ADDR 0xff00810c
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#define LMAR1_ADDR 0xff008110
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#define LMMR1_ADDR 0xff008114
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#define IPB0_ADDR 0xff008400
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#define IPB1_ADDR 0xff008404
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#define DAB0_ADDR 0xff008420
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#define DAB1_ADDR 0xff008424
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#define BPCON_ADDR 0xff008440
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#define IPND_ADDR 0xff008500
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#define IMSK_ADDR 0xff008504
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#define ICON_ADDR 0xff008510
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#define IMAP0_ADDR 0xff008520
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#define IMAP1_ADDR 0xff008524
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#define IMAP2_ADDR 0xff008528
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#define PMCON0_ADDR 0xff008600
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#define PMCON2_ADDR 0xff008608
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#define PMCON4_ADDR 0xff008610
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#define PMCON6_ADDR 0xff008618
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#define PMCON8_ADDR 0xff008620
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#define PMCON10_ADDR 0xff008628
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#define PMCON12_ADDR 0xff008630
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#define PMCON14_ADDR 0xff008638
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#define BCON_ADDR 0xff0086fc
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#define PRCB_ADDR 0xff008700
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#define ISP_ADDR 0xff008704
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#define SSP_ADDR 0xff008708
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#define DEVID_ADDR 0xff008710
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#define TRR0_ADDR 0xff000300
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#define TCR0_ADDR 0xff000304
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#define TMR0_ADDR 0xff000308
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#define TRR1_ADDR 0xff000310
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#define TCR1_ADDR 0xff000314
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#define TMR1_ADDR 0xff000318
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/* RP-only addresses: */
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/* RP MMRs */
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/* PCI-to-PCI Bridge Unit 0000 1000H through 0000 10FFH */
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#define VIDR_ADDR 0x00001000
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#define DIDR_ADDR 0x00001002
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#define PCMDR_ADDR 0x00001004
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#define PSR_ADDR 0x00001006
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#define RIDR_ADDR 0x00001008
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#define CCR_ADDR 0x00001009
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#define CLSR_ADDR 0x0000100C
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#define PLTR_ADDR 0x0000100D
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#define HTR_ADDR 0x0000100E
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/* Reserved 0x0000100F through 0x00001017 */
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#define PBNR_ADDR 0x00001018
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#define SBNR_ADDR 0x00001019
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#define SUBBNR_ADDR 0x0000101A
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#define SLTR_ADDR 0x0000101B
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#define IOBR_ADDR 0x0000101C
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#define IOLR_ADDR 0x0000101D
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#define SSR_ADDR 0x0000101E
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#define MBR_ADDR 0x00001020
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#define MLR_ADDR 0x00001022
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#define PMBR_ADDR 0x00001024
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#define PMLR_ADDR 0x00001026
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/* Reserved 0x00001028 through 0x00001033 */
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#define BSVIR_ADDR 0x00001034
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#define BSIR_ADDR 0x00001036
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/* Reserved 0x00001038 through 0x0000103D */
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#define BCR_ADDR 0x0000103E
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#define EBCR_ADDR 0x00001040
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#define SISR_ADDR 0x00001042
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#define PBISR_ADDR 0x00001044
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#define SBISR_ADDR 0x00001048
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#define SACR_ADDR 0x0000104C
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#define PIRSR_ADDR 0x00001050
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#define SIOBR_ADDR 0x00001054
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#define SIOLR_ADDR 0x00001055
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#define SMBR_ADDR 0x00001058
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#define SMLR_ADDR 0x0000105A
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#define SDER_ADDR 0x0000105C
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/* Reserved 0x0000105E through 0x000011FFH */
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/* Address Translation Unit 0000 1200H through 0000 12FFH */
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#define ATUVID_ADDR 0x00001200
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#define ATUDID_ADDR 0x00001202
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#define PATUCMD_ADDR 0x00001204
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#define PATUSR_ADDR 0x00001206
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#define ATURID_ADDR 0x00001208
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#define ATUCCR_ADDR 0x00001209
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#define ATUCLSR_ADDR 0x0000120C
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#define ATULT_ADDR 0x0000120D
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#define ATUHTR_ADDR 0x0000120E
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#define ATUBISTR_ADDR 0x0000120F
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#define PIABAR_ADDR 0x00001210
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/* Reserved 0x00001214 */
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/* Reserved 0x00001218 */
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/* Reserved 0x0000121C */
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/* Reserved 0x00001220 */
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/* Reserved 0x00001224 */
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/* Reserved 0x00001228 */
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#define ASVIR_ADDR 0x0000122C
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#define ASIR_ADDR 0x0000122E
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#define ERBAR_ADDR 0x00001230
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/* Reserved 0x00001234 */
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/* Reserved 0x00001238 */
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#define ATUILR_ADDR 0x0000123C
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#define ATUIPR_ADDR 0x0000123D
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#define ATUMGNT_ADDR 0x0000123E
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#define ATUMLAT_ADDR 0x0000123F
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#define PIALR_ADDR 0x00001240
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#define PIATVR_ADDR 0x00001244
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#define SIABAR_ADDR 0x00001248
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#define SIALR_ADDR 0x0000124C
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#define SIATVR_ADDR 0x00001250
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#define POMWVR_ADDR 0x00001254
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/* Reserved 0x00001258 */
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#define POIOWVR_ADDR 0x0000125C
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#define PODWVR_ADDR 0x00001260
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#define POUDR_ADDR 0x00001264
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#define SOMWVR_ADDR 0x00001268
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#define SOIOWVR_ADDR 0x0000126C
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/* Reserved 0x00001270 */
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#define ERLR_ADDR 0x00001274
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#define ERTVR_ADDR 0x00001278
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/* Reserved 0x0000127C */
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/* Reserved 0x00001280 */
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/* Reserved 0x00001284 */
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#define ATUCR_ADDR 0x00001288
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/* Reserved 0x0000128C */
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#define PATUISR_ADDR 0x00001290
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#define SATUISR_ADDR 0x00001294
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#define SATUCMD_ADDR 0x00001298
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#define SATUSR_ADDR 0x0000129A
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#define SODWVR_ADDR 0x0000129C
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#define SOUDR_ADDR 0x000012A0
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#define POCCAR_ADDR 0x000012A4
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#define SOCCAR_ADDR 0x000012A8
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#define POCCDR_ADDR 0x000012AC
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#define SOCCDR_ADDR 0x000012B0
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/* Reserved 0x000012B4 through 0x000012FF */
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/* Messaging Unit 0000 1300H through 0000 13FFH */
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#define ARSR_ADDR 0x00001300
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/* Reserved 0x00001304 */
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#define AWR_ADDR 0x00001308
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/* Reserved 0x0000130C */
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#define IMR0_ADDR 0x00001310
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#define IMR1_ADDR 0x00001314
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#define OMR0_ADDR 0x00001318
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#define OMR1_ADDR 0x0000131C
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#define IDR_ADDR 0x00001320
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#define IISR_ADDR 0x00001324
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#define IIMR_ADDR 0x00001328
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#define ODR_ADDR 0x0000132C
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#define OISR_ADDR 0x00001330
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#define OIMR_ADDR 0x00001334
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/* Reserved 0x00001338 through 0x0000134F */
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#define MUCR_ADDR 0x00001350
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#define QBAR_ADDR 0x00001354
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/* Reserved 0x00001358 */
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/* Reserved 0x0000135C */
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#define IFHPR_ADDR 0x00001360
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#define IFTPR_ADDR 0x00001364
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#define IPHPR_ADDR 0x00001368
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#define IPTPR_ADDR 0x0000136C
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#define OFHPR_ADDR 0x00001370
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#define OFTPR_ADDR 0x00001374
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#define OPHPR_ADDR 0x00001378
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#define OPTPR_ADDR 0x0000137C
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#define IAR_ADDR 0x00001380
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/* Reserved 0x00001384 through 0x000013FF */
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/* DMA Controller 0000 1400H through 0000 14FFH */
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#define CCR0_ADDR 0x00001400
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#define CSR0_ADDR 0x00001404
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/* Reserved 0x00001408 */
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#define DAR0_ADDR 0x0000140C
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#define NDAR0_ADDR 0x00001410
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#define PADR0_ADDR 0x00001414
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#define PUADR0_ADDR 0x00001418
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#define LADR0_ADDR 0x0000141C
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#define BCR0_ADDR 0x00001420
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#define DCR0_ADDR 0x00001424
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/* Reserved 0x00001428 through 0x0000143F */
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#define CCR1_ADDR 0x00001440
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#define CSR1_ADDR 0x00001444
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/* Reserved 0x00001448 */
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#define DAR1_ADDR 0x0000144C
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#define NDAR1_ADDR 0x00001450
|
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#define PADR1_ADDR 0x00001454
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#define PUADR1_ADDR 0x00001458
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#define LADR1_ADDR 0x0000145C
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#define BCR1_ADDR 0x00001460
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#define DCR1_ADDR 0x00001464
|
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/* Reserved 0x00001468 through 0x0000147F */
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#define CCR2_ADDR 0x00001480
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#define CSR2_ADDR 0x00001484
|
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/* Reserved 0x00001488 */
|
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#define DAR2_ADDR 0x0000148C
|
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#define NDAR2_ADDR 0x00001490
|
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#define PADR2_ADDR 0x00001494
|
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#define PUADR2_ADDR 0x00001498
|
||||
#define LADR2_ADDR 0x0000149C
|
||||
#define BCR2_ADDR 0x000014A0
|
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#define DCR2_ADDR 0x000014A4
|
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/* Reserved 0x000014A8 through 0x000014FF */
|
||||
|
||||
/* Memory Controller 0000 1500H through 0000 15FFH */
|
||||
#define MBCR_ADDR 0x00001500
|
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#define MBBAR0_ADDR 0x00001504
|
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#define MBRWS0_ADDR 0x00001508
|
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#define MBWWS0_ADDR 0x0000150C
|
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#define MBBAR1_ADDR 0x00001510
|
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#define MBRWS1_ADDR 0x00001514
|
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#define MBWWS1_ADDR 0x00001518
|
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#define DBCR_ADDR 0x0000151C
|
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#define DBAR_ADDR 0x00001520
|
||||
#define DRWS_ADDR 0x00001524
|
||||
#define DWWS_ADDR 0x00001528
|
||||
#define DRIR_ADDR 0x0000152C
|
||||
#define DPER_ADDR 0x00001530
|
||||
#define BMER_ADDR 0x00001534
|
||||
#define MEAR_ADDR 0x00001538
|
||||
#define LPISR_ADDR 0x0000153C
|
||||
/* Reserved 0x00001540 through 0x000015FF */
|
||||
|
||||
/* Local Bus Arbitration Unit 0000 1600H through 0000 167FH
|
||||
*/
|
||||
#define LBACR_ADDR 0x00001600
|
||||
#define LBALCR_ADDR 0x00001604
|
||||
/* Reserved 0x00001608 through 0x0000167F */
|
||||
|
||||
/* I2C Bus Interface Unit 0000 1680H through 0000 16FFH */
|
||||
#define ICR_ADDR 0x00001680
|
||||
#define ISR_ADDR 0x00001684
|
||||
#define ISAR_ADDR 0x00001688
|
||||
#define IDBR_ADDR 0x0000168C
|
||||
#define ICCR_ADDR 0x00001690
|
||||
/* Reserved 0x00001694 through 0x000016FF */
|
||||
|
||||
/* PCI And Peripheral Interrupt Controller 0000 1700H through
|
||||
0000 177FH */
|
||||
#define NISR_ADDR 0x00001700
|
||||
#define X7ISR_ADDR 0x00001704
|
||||
#define X6ISR_ADDR 0x00001708
|
||||
#define PDDIR_ADDR 0x00001710
|
||||
/* Reserved 0x00001714 through 0x0000177F */
|
||||
|
||||
/* APIC Bus Interface Unit 0000 1780H through 0000 17FFH */
|
||||
#define APICIDR_ADDR 0x00001780
|
||||
#define APICARBID_ADDR 0x00001784
|
||||
#define EVR_ADDR 0x00001788
|
||||
#define IMR_ADDR 0x0000178C
|
||||
#define APICCSR_ADDR 0x00001790
|
||||
/* Reserved 0x00001794 through 0x000017FF */
|
||||
|
||||
/* Byte order bit for region configuration */
|
||||
/* Set to Little Endian for the 80960RP*/
|
||||
#define I960RP_BYTE_ORDER I960RP_BIG_ENDIAN(0)
|
||||
#define I960RP_BUS_WIDTH(bw) ((bw==16)?(1<<22):(0)) | ((bw==32)?(2<<22):(0))
|
||||
#define I960RP_BIG_ENDIAN(on) ((on)?(0x1<<31):0)
|
||||
#define I960RP_BYTE_N(n,data) (((unsigned)(data) >> (n*8)) & 0xFF)
|
||||
#define I960RP_BUS_WIDTH_8 0
|
||||
#define I960RP_BUS_WIDTH_16 (1<<22)
|
||||
#define I960RP_BUS_WIDTH_32 (1<<23)
|
||||
|
||||
|
||||
/* ATU Register Definitions */
|
||||
|
||||
#define ATUCR_SECOUTEN 0x4
|
||||
#define ATUCR_PRIOUTEN 0x2
|
||||
#define ATUCR_DADRSELEN 0x100
|
||||
#define ATUCR_SECDADREN 0x80
|
||||
#define AUTCR_SECERRINTEN 0x20
|
||||
#define AUTCR_PRIERRINTEN 0x10
|
||||
|
||||
#define ATUSCMD_IOEN 0x1
|
||||
#define ATUSCMD_MEMEN 0x2
|
||||
#define ATUSCMD_BUSMSTEN 0x4
|
||||
|
||||
#define ATUPCMD_IOEN 0x1
|
||||
#define ATUPCMD_MEMEN 0x2
|
||||
#define ATUPCMD_BUSMSTEN 0x4
|
||||
|
||||
/* EBCR Register Definitions */
|
||||
#define EBCR_CCR_MASK 0x4
|
||||
|
||||
#define rp_readreg32( x) ( *((unsigned int *) x))
|
||||
#define rp_writereg32( x, v) ( *((unsigned int *) x) = v)
|
||||
#define rp_readreg16( x) ( *((unsigned short *) x))
|
||||
#define rp_writereg16( x, v) ( *((unsigned short *) x) = v)
|
||||
#define rp_readreg8( x) ( *((unsigned char *) x))
|
||||
#define rp_writereg8( x, v) ( *((unsigned char *) x) = v)
|
||||
|
||||
|
||||
/* i960 Memory Map values */
|
||||
|
||||
#define RP_PRI_IO_WIND_BASE 0x90000000
|
||||
#define RP_SEC_IO_WIND_BASE 0x90010000
|
||||
#define RP_SEC_MEM_WIND_BASE 0x88000000
|
||||
#define RP_PRI_MEM_WIND_BASE 0x80000000
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
@@ -165,8 +165,6 @@ typedef struct {
|
||||
void * (*stack_allocate_hook)( unsigned32 );
|
||||
void (*stack_free_hook)( void* );
|
||||
/* end of fields required on all CPUs */
|
||||
|
||||
i960_PRCB *Prcb;
|
||||
} rtems_cpu_table;
|
||||
|
||||
/*
|
||||
@@ -176,11 +174,10 @@ typedef struct {
|
||||
|
||||
/*
|
||||
* Macros to access i960 specific additions to the CPU Table
|
||||
*
|
||||
* NONE
|
||||
*/
|
||||
|
||||
#define rtems_cpu_configuration_get_prcb() \
|
||||
(_CPU_Table.Prcb)
|
||||
|
||||
/* variables */
|
||||
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
|
||||
|
||||
@@ -33,314 +33,60 @@ extern "C" {
|
||||
* NOTE: RTEMS defines a canonical name for each cpu model.
|
||||
*/
|
||||
|
||||
#if defined(rtems_multilib)
|
||||
/*
|
||||
* Figure out all CPU Model Feature Flags based upon compiler
|
||||
* predefines.
|
||||
*/
|
||||
|
||||
#define CPU_MODEL_NAME "rtems_multilib"
|
||||
#define I960_HAS_FPU 0
|
||||
#define I960_CPU_ALIGNMENT 4
|
||||
#define I960_SOFT_RESET_COMMAND 0x30000
|
||||
|
||||
#elif defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
|
||||
|
||||
#define CPU_MODEL_NAME "i960ca"
|
||||
#define __RTEMS_I960CA__
|
||||
|
||||
#elif defined(__i960KA__)
|
||||
#define CPU_MODEL_NAME "i960ka"
|
||||
|
||||
#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
|
||||
|
||||
#define CPU_MODEL_NAME "i960ha"
|
||||
#define __RTEMS_I960HA__
|
||||
|
||||
#elif defined(__i960RP__)
|
||||
|
||||
#include <i960RP.h>
|
||||
#define CPU_MODEL_NAME "i960rp"
|
||||
#define __RTEMS_I960RP__
|
||||
#define I960_CPU_ALIGNMENT 8
|
||||
#define I960_SOFT_RESET_COMMAND 0x300
|
||||
|
||||
#else
|
||||
|
||||
#error "Unsupported CPU Model"
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Now default some CPU model variation parameters
|
||||
*/
|
||||
|
||||
#ifndef I960_HAS_FPU
|
||||
#define I960_HAS_FPU 0
|
||||
#endif
|
||||
|
||||
#ifndef I960_CPU_ALIGNMENT
|
||||
#define I960_CPU_ALIGNMENT 4
|
||||
#endif
|
||||
|
||||
#ifndef I960_SOFT_RESET_COMMAND
|
||||
#define I960_SOFT_RESET_COMMAND 0x30000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define the name of the CPU family.
|
||||
*/
|
||||
|
||||
#define CPU_NAME "Intel i960"
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
/*
|
||||
* XXX should have an ifdef here and have stuff for the other
|
||||
* XXX family members...
|
||||
*/
|
||||
|
||||
#if defined(__RTEMS_I960CA__)
|
||||
/*
|
||||
* Now default some CPU model variation parameters
|
||||
* This should work since most i960 models do not have FPUs. The logic is:
|
||||
*
|
||||
* + If the user specifically asks for soft-float, give it to them
|
||||
* regardless of hardware availability.
|
||||
* + If the CPU has hardware FPU, then use it.
|
||||
* + Otherwise, we have to use soft float.
|
||||
*/
|
||||
|
||||
#ifndef I960_HAS_FPU
|
||||
#if defined(_SOFT_FLOAT)
|
||||
#define I960_HAS_FPU 0
|
||||
#elif defined(_i960_KB__) || defined(_i960_SB__) || defined(_i960_SB__) || \
|
||||
defined(_i960_JF__) || defined(_i960_MC__) || defined(_i960_CC__)
|
||||
#define I960_HAS_FPU 1
|
||||
#else
|
||||
#define I960_HAS_FPU 0
|
||||
#endif
|
||||
|
||||
#ifndef I960_CPU_ALIGNMENT
|
||||
/*
|
||||
* Some of the CPU models may have better performance with
|
||||
* alignment of 8 or 16 but we don't know what model we are
|
||||
* being compiled for based solely on the information provided
|
||||
* when multilibbing.
|
||||
*/
|
||||
|
||||
#define I960_CPU_ALIGNMENT 4
|
||||
#endif
|
||||
|
||||
|
||||
/* i960CA control structures */
|
||||
|
||||
/* Intel i960CA Control Table */
|
||||
|
||||
typedef struct {
|
||||
/* Control Group 0 */
|
||||
unsigned int ipb0; /* IP breakpoint 0 */
|
||||
unsigned int ipb1; /* IP breakpoint 1 */
|
||||
unsigned int dab0; /* data address breakpoint 0 */
|
||||
unsigned int dab1; /* data address breakpoint 1 */
|
||||
/* Control Group 1 */
|
||||
unsigned int imap0; /* interrupt map 0 */
|
||||
unsigned int imap1; /* interrupt map 1 */
|
||||
unsigned int imap2; /* interrupt map 2 */
|
||||
unsigned int icon; /* interrupt control */
|
||||
/* Control Group 2 */
|
||||
unsigned int mcon0; /* memory region 0 configuration */
|
||||
unsigned int mcon1; /* memory region 1 configuration */
|
||||
unsigned int mcon2; /* memory region 2 configuration */
|
||||
unsigned int mcon3; /* memory region 3 configuration */
|
||||
/* Control Group 3 */
|
||||
unsigned int mcon4; /* memory region 4 configuration */
|
||||
unsigned int mcon5; /* memory region 5 configuration */
|
||||
unsigned int mcon6; /* memory region 6 configuration */
|
||||
unsigned int mcon7; /* memory region 7 configuration */
|
||||
/* Control Group 4 */
|
||||
unsigned int mcon8; /* memory region 8 configuration */
|
||||
unsigned int mcon9; /* memory region 9 configuration */
|
||||
unsigned int mcon10; /* memory region 10 configuration */
|
||||
unsigned int mcon11; /* memory region 11 configuration */
|
||||
/* Control Group 5 */
|
||||
unsigned int mcon12; /* memory region 12 configuration */
|
||||
unsigned int mcon13; /* memory region 13 configuration */
|
||||
unsigned int mcon14; /* memory region 14 configuration */
|
||||
unsigned int mcon15; /* memory region 15 configuration */
|
||||
/* Control Group 6 */
|
||||
unsigned int reserved; /* reserved */
|
||||
unsigned int bpcon; /* breakpoint control */
|
||||
unsigned int tc; /* trace control */
|
||||
unsigned int bcon; /* bus configuration control */
|
||||
} i960ca_control_table;
|
||||
|
||||
/* Intel i960CA Processor Control Block */
|
||||
|
||||
typedef struct {
|
||||
unsigned int *fault_tbl; /* fault table base address */
|
||||
i960ca_control_table
|
||||
*control_tbl; /* control table base address */
|
||||
unsigned int initial_ac; /* AC register initial value */
|
||||
unsigned int fault_config; /* fault configuration word */
|
||||
void **intr_tbl; /* interrupt table base address */
|
||||
void *sys_proc_tbl; /* system procedure table
|
||||
base address */
|
||||
unsigned int reserved; /* reserved */
|
||||
unsigned int *intr_stack; /* interrupt stack pointer */
|
||||
unsigned int ins_cache_cfg; /* instruction cache
|
||||
configuration word */
|
||||
unsigned int reg_cache_cfg; /* register cache configuration word */
|
||||
} i960ca_PRCB;
|
||||
|
||||
typedef i960ca_control_table i960_control_table;
|
||||
typedef i960ca_PRCB i960_PRCB;
|
||||
|
||||
#elif defined(__RTEMS_I960HA__)
|
||||
|
||||
/* i960HA control structures */
|
||||
|
||||
/* Intel i960HA Control Table */
|
||||
|
||||
typedef struct {
|
||||
/* Control Group 0 */
|
||||
unsigned int ipb0; /* IP breakpoint 0 */
|
||||
unsigned int ipb1; /* IP breakpoint 1 */
|
||||
unsigned int dab0; /* data address breakpoint 0 */
|
||||
unsigned int dab1; /* data address breakpoint 1 */
|
||||
/* Control Group 1 */
|
||||
unsigned int imap0; /* interrupt map 0 */
|
||||
unsigned int imap1; /* interrupt map 1 */
|
||||
unsigned int imap2; /* interrupt map 2 */
|
||||
unsigned int icon; /* interrupt control */
|
||||
/* Control Group 2 */
|
||||
unsigned int mcon0; /* memory region 0 configuration */
|
||||
unsigned int mcon1; /* memory region 1 configuration */
|
||||
unsigned int mcon2; /* memory region 2 configuration */
|
||||
unsigned int mcon3; /* memory region 3 configuration */
|
||||
/* Control Group 3 */
|
||||
unsigned int mcon4; /* memory region 4 configuration */
|
||||
unsigned int mcon5; /* memory region 5 configuration */
|
||||
unsigned int mcon6; /* memory region 6 configuration */
|
||||
unsigned int mcon7; /* memory region 7 configuration */
|
||||
/* Control Group 4 */
|
||||
unsigned int mcon8; /* memory region 8 configuration */
|
||||
unsigned int mcon9; /* memory region 9 configuration */
|
||||
unsigned int mcon10; /* memory region 10 configuration */
|
||||
unsigned int mcon11; /* memory region 11 configuration */
|
||||
/* Control Group 5 */
|
||||
unsigned int mcon12; /* memory region 12 configuration */
|
||||
unsigned int mcon13; /* memory region 13 configuration */
|
||||
unsigned int mcon14; /* memory region 14 configuration */
|
||||
unsigned int mcon15; /* memory region 15 configuration */
|
||||
/* Control Group 6 */
|
||||
unsigned int reserved; /* reserved */
|
||||
unsigned int bpcon; /* breakpoint control */
|
||||
unsigned int tc; /* trace control */
|
||||
unsigned int bcon; /* bus configuration control */
|
||||
} i960ha_control_table;
|
||||
|
||||
/* Intel i960HA Processor Control Block */
|
||||
|
||||
typedef struct {
|
||||
unsigned int *fault_tbl; /* fault table base address */
|
||||
i960ha_control_table
|
||||
*control_tbl; /* control table base address */
|
||||
unsigned int initial_ac; /* AC register initial value */
|
||||
unsigned int fault_config; /* fault configuration word */
|
||||
void **intr_tbl; /* interrupt table base address */
|
||||
void *sys_proc_tbl; /* system procedure table
|
||||
base address */
|
||||
unsigned int reserved; /* reserved */
|
||||
unsigned int *intr_stack; /* interrupt stack pointer */
|
||||
unsigned int ins_cache_cfg; /* instruction cache
|
||||
configuration word */
|
||||
unsigned int reg_cache_cfg; /* register cache configuration word */
|
||||
} i960ha_PRCB;
|
||||
|
||||
typedef i960ha_control_table i960_control_table;
|
||||
typedef i960ha_PRCB i960_PRCB;
|
||||
|
||||
#elif defined(__RTEMS_I960RP__)
|
||||
|
||||
/* i960RP control structures */
|
||||
|
||||
/* Intel i960RP Control Table */
|
||||
|
||||
typedef struct {
|
||||
/* Control Group 0 */
|
||||
unsigned int rsvd00;
|
||||
unsigned int rsvd01;
|
||||
unsigned int rsvd02;
|
||||
unsigned int rsvd03;
|
||||
/* Control Group 1 */
|
||||
unsigned int imap0; /* interrupt map 0 */
|
||||
unsigned int imap1; /* interrupt map 1 */
|
||||
unsigned int imap2; /* interrupt map 2 */
|
||||
unsigned int icon; /* interrupt control */
|
||||
/* Control Group 2 */
|
||||
unsigned int pmcon0; /* memory region 0 configuration */
|
||||
unsigned int rsvd1;
|
||||
unsigned int pmcon2; /* memory region 2 configuration */
|
||||
unsigned int rsvd2;
|
||||
/* Control Group 3 */
|
||||
unsigned int pmcon4; /* memory region 4 configuration */
|
||||
unsigned int rsvd3;
|
||||
unsigned int pmcon6; /* memory region 6 configuration */
|
||||
unsigned int rsvd4;
|
||||
/* Control Group 4 */
|
||||
unsigned int pmcon8; /* memory region 8 configuration */
|
||||
unsigned int rsvd5;
|
||||
unsigned int pmcon10; /* memory region 10 configuration */
|
||||
unsigned int rsvd6;
|
||||
/* Control Group 5 */
|
||||
unsigned int pmcon12; /* memory region 12 configuration */
|
||||
unsigned int rsvd7;
|
||||
unsigned int pmcon14; /* memory region 14 configuration */
|
||||
unsigned int rsvd8;
|
||||
/* Control Group 6 */
|
||||
unsigned int rsvd9;
|
||||
unsigned int rsvd10;
|
||||
unsigned int tc; /* trace control */
|
||||
unsigned int bcon; /* bus configuration control */
|
||||
} i960rp_control_table;
|
||||
|
||||
/* Intel i960RP Processor Control Block */
|
||||
|
||||
typedef struct {
|
||||
unsigned int *fault_tbl; /* fault table base address */
|
||||
i960rp_control_table
|
||||
*control_tbl; /* control table base address */
|
||||
unsigned int initial_ac; /* AC register initial value */
|
||||
unsigned int fault_config; /* fault configuration word */
|
||||
void **intr_tbl; /* interrupt table base address */
|
||||
void *sys_proc_tbl; /* system procedure table
|
||||
base address */
|
||||
unsigned int reserved; /* reserved */
|
||||
unsigned int *intr_stack; /* interrupt stack pointer */
|
||||
unsigned int ins_cache_cfg; /* instruction cache
|
||||
configuration word */
|
||||
unsigned int reg_cache_cfg; /* register cache configuration word */
|
||||
} i960rp_PRCB;
|
||||
|
||||
typedef i960rp_control_table i960_control_table;
|
||||
typedef i960rp_PRCB i960_PRCB;
|
||||
|
||||
#elif defined(__i960KA__)
|
||||
|
||||
/* i960KA control structures */
|
||||
|
||||
/* Intel i960KA Control Table */
|
||||
|
||||
typedef struct {
|
||||
int pad0;
|
||||
} i960ka_control_table;
|
||||
|
||||
/* Intel i960KA Processor Control Block */
|
||||
|
||||
typedef struct {
|
||||
void **intr_tbl; /* interrupt table base address */
|
||||
unsigned int *intr_stack; /* interrupt stack pointer */
|
||||
} i960ka_PRCB;
|
||||
|
||||
typedef i960ka_control_table i960_control_table;
|
||||
typedef i960ka_PRCB i960_PRCB;
|
||||
/*
|
||||
* This is not the perfect CPU model name but it is adequate and
|
||||
* reflects what we know from multilib.
|
||||
*/
|
||||
|
||||
#if I960_HAS_FPU
|
||||
#define CPU_MODEL_NAME "i960 w/FPU"
|
||||
#else
|
||||
#error "invalid processor selection!"
|
||||
#define CPU_MODEL_NAME "i960 w/soft-float"
|
||||
#endif
|
||||
#ifndef ASM
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous Support Routines
|
||||
*/
|
||||
|
||||
#if !defined(__i960KA__)
|
||||
#define i960_reload_ctl_group( group ) \
|
||||
{ register int _cmd = ((group)|0x400) ; \
|
||||
asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
|
||||
}
|
||||
#endif
|
||||
|
||||
#define i960_atomic_modify( mask, addr, prev ) \
|
||||
{ register unsigned int _mask = (mask); \
|
||||
@@ -393,123 +139,21 @@ typedef i960ka_PRCB i960_PRCB;
|
||||
(_level) = ((_level) & 0x1f0000) >> 16; \
|
||||
} while ( 0 )
|
||||
|
||||
#if !defined(__i960KA__)
|
||||
#define i960_cause_intr( intr ) \
|
||||
{ register int _intr = (intr); \
|
||||
asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Interrupt Masking Routines
|
||||
*/
|
||||
|
||||
#if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__)
|
||||
|
||||
#define i960_unmask_intr( xint ) \
|
||||
{ register unsigned int _mask= (1<<(xint)); \
|
||||
asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
|
||||
}
|
||||
|
||||
#define i960_mask_intr( xint ) \
|
||||
{ register unsigned int _mask= (1<<(xint)); \
|
||||
asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
|
||||
}
|
||||
|
||||
#define i960_clear_intr( xint ) \
|
||||
{ register unsigned int _xint=(xint); \
|
||||
asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \
|
||||
bbs %0,sf0, loop_til_cleared" \
|
||||
: "=d" (_xint) : "0" (_xint) ); \
|
||||
}
|
||||
|
||||
static inline unsigned int i960_pend_intrs()
|
||||
{ register unsigned int _intr=0;
|
||||
asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
|
||||
return ( _intr );
|
||||
}
|
||||
|
||||
static inline unsigned int i960_mask_intrs()
|
||||
{ register unsigned int _intr=0;
|
||||
asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
|
||||
return( _intr );
|
||||
}
|
||||
|
||||
#elif defined(__RTEMS_I960RP__)
|
||||
|
||||
#define i960_unmask_intr( xint ) \
|
||||
{ register unsigned int _mask= (1<<(xint)); \
|
||||
register unsigned int *_imsk = (int * ) IMSK_ADDR; \
|
||||
register unsigned int _val= *_imsk; \
|
||||
asm volatile( "or %0,%2,%0; \
|
||||
st %0,(%1)" \
|
||||
: "=d" (_val), "=d" (_imsk), "=d" (_mask) \
|
||||
: "0" (_val), "1" (_imsk), "2" (_mask) ); \
|
||||
}
|
||||
|
||||
#define i960_mask_intr( xint ) \
|
||||
{ register unsigned int _mask= (1<<(xint)); \
|
||||
register unsigned int *_imsk = (int * ) IMSK_ADDR; \
|
||||
register unsigned int _val = *_imsk; \
|
||||
asm volatile( "andnot %2,%0,%0; \
|
||||
st %0,(%1)" \
|
||||
: "=d" (_val), "=d" (_imsk), "=d" (_mask) \
|
||||
: "0" (_val), "1" (_imsk), "2" (_mask) ); \
|
||||
}
|
||||
#define i960_clear_intr( xint ) \
|
||||
{ register unsigned int _xint=xint; \
|
||||
register unsigned int _mask=(1<<(xint)); \
|
||||
register unsigned int *_ipnd = (int * ) IPND_ADDR; \
|
||||
register unsigned int _rslt = 0; \
|
||||
asm volatile( "loop_til_cleared: mov 0, %0; \
|
||||
atmod %1, %2, %0; \
|
||||
bbs %3,%0, loop_til_cleared" \
|
||||
: "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \
|
||||
: "0" (_rslt), "1" (_ipnd), "2" (_mask), "3" (_xint) ); \
|
||||
}
|
||||
|
||||
static inline unsigned int i960_pend_intrs()
|
||||
{ register unsigned int _intr= *(unsigned int *) IPND_ADDR;
|
||||
/*register unsigned int *_ipnd = (int * ) IPND_ADDR; \
|
||||
asm volatile( "mov (%0),%1" \
|
||||
: "=d" (_ipnd), "=d" (_mask) \
|
||||
: "0" (_ipnd), "1" (_mask) ); \ */
|
||||
return ( _intr );
|
||||
}
|
||||
|
||||
static inline unsigned int i960_mask_intrs()
|
||||
{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR;
|
||||
/*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/
|
||||
return( _intr );
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline unsigned int i960_get_fp()
|
||||
{ register unsigned int _fp=0;
|
||||
asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
|
||||
return ( _fp );
|
||||
}
|
||||
|
||||
/*
|
||||
* Soft Reset
|
||||
*/
|
||||
|
||||
#if defined(I960_SOFT_RESET_COMMAND)
|
||||
#define i960_soft_reset( prcb ) \
|
||||
{ register i960_PRCB *_prcb = (prcb); \
|
||||
register unsigned int *_next=0; \
|
||||
register unsigned int _cmd = I960_SOFT_RESET_COMMAND; \
|
||||
asm volatile( "lda next,%1; \
|
||||
sysctl %0,%1,%2; \
|
||||
next: mov g0,g0" \
|
||||
: "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
|
||||
: "0" (_cmd), "1" (_next), "2" (_prcb) ); \
|
||||
}
|
||||
|
||||
#elif !defined(__i960KA__)
|
||||
#warning "I960_SOFT_RESET_COMMAND is not defined"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following routine swaps the endian format of an unsigned int.
|
||||
* It must be static because it is referenced indirectly.
|
||||
|
||||
Reference in New Issue
Block a user