forked from Imagelibrary/rtems
leon, grcan: consistent indentation
This commit does not contain any change of functionality.
This commit is contained in:
committed by
Daniel Hellstrom
parent
ad203e5887
commit
bc40b4def8
@@ -389,14 +389,14 @@ static rtems_device_driver grcan_hw_start(struct grcan_priv *pDev)
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FUNCDBG();
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/* Check that memory has been allocated successfully */
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if ( !pDev->tx || !pDev->rx )
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if (!pDev->tx || !pDev->rx)
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return RTEMS_NO_MEMORY;
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/* Configure FIFO configuration register
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* and Setup timing
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*/
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if ( pDev->config_changed ){
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grcan_hw_config(pDev->regs,&pDev->config);
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if (pDev->config_changed) {
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grcan_hw_config(pDev->regs, &pDev->config);
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pDev->config_changed = 0;
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}
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@@ -409,10 +409,10 @@ static rtems_device_driver grcan_hw_start(struct grcan_priv *pDev)
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pDev->regs->tx0size = pDev->txbuf_size;
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/* Setup acceptance filters */
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grcan_hw_accept(pDev->regs,&pDev->afilter);
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grcan_hw_accept(pDev->regs, &pDev->afilter);
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/* Sync filters */
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grcan_hw_sync(pDev->regs,&pDev->sfilter);
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grcan_hw_sync(pDev->regs, &pDev->sfilter);
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/* Clear status bits */
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tmp = READ_REG(&pDev->regs->stat);
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@@ -429,14 +429,14 @@ static rtems_device_driver grcan_hw_start(struct grcan_priv *pDev)
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/* Enable routing of the IRQs */
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IRQ_GLOBAL_DISABLE(oldLevel);
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IRQ_UNMASK(pDev->irq+GRCAN_IRQ_TXSYNC);
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IRQ_UNMASK(pDev->irq+GRCAN_IRQ_RXSYNC);
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IRQ_UNMASK(pDev->irq+GRCAN_IRQ_IRQ);
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IRQ_UNMASK(pDev->irq + GRCAN_IRQ_TXSYNC);
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IRQ_UNMASK(pDev->irq + GRCAN_IRQ_RXSYNC);
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IRQ_UNMASK(pDev->irq + GRCAN_IRQ_IRQ);
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IRQ_GLOBAL_ENABLE(oldLevel);
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/* Reset some software data */
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/*pDev->txerror = 0;
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pDev->rxerror = 0;*/
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pDev->rxerror = 0; */
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/* Enable receiver/transmitter */
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pDev->regs->rx0ctrl = GRCAN_RXCTRL_ENABLE;
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@@ -457,9 +457,9 @@ static void grcan_hw_stop(struct grcan_priv *pDev)
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/* Mask all IRQs */
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pDev->regs->imr = 0;
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IRQ_MASK(pDev->irq+GRCAN_IRQ_TXSYNC);
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IRQ_MASK(pDev->irq+GRCAN_IRQ_RXSYNC);
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IRQ_MASK(pDev->irq+GRCAN_IRQ_IRQ);
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IRQ_MASK(pDev->irq + GRCAN_IRQ_TXSYNC);
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IRQ_MASK(pDev->irq + GRCAN_IRQ_RXSYNC);
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IRQ_MASK(pDev->irq + GRCAN_IRQ_IRQ);
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/* Disable receiver & transmitter */
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pDev->regs->rx0ctrl = 0;
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@@ -476,37 +476,35 @@ static void grcan_hw_stop(struct grcan_priv *pDev)
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rtems_semaphore_flush(pDev->txempty_sem);
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}
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static void grcan_hw_config(
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struct grcan_regs *regs,
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struct grcan_config *conf
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)
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static void grcan_hw_config(struct grcan_regs *regs, struct grcan_config *conf)
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{
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unsigned int config=0;
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unsigned int config = 0;
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/* Reset HurriCANe Core */
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regs->ctrl = 0;
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if ( conf->silent )
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if (conf->silent)
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config |= GRCAN_CFG_SILENT;
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if ( conf->abort )
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if (conf->abort)
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config |= GRCAN_CFG_ABORT;
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if ( conf->selection.selection )
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if (conf->selection.selection)
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config |= GRCAN_CFG_SELECTION;
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if ( conf->selection.enable0 )
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if (conf->selection.enable0)
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config |= GRCAN_CFG_ENABLE0;
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if ( conf->selection.enable1 )
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if (conf->selection.enable1)
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config |= GRCAN_CFG_ENABLE1;
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/* Timing */
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config |= (conf->timing.bpr<<GRCAN_CFG_BPR_BIT) & GRCAN_CFG_BPR;
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config |= (conf->timing.rsj<<GRCAN_CFG_RSJ_BIT) & GRCAN_CFG_RSJ;
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config |= (conf->timing.ps1<<GRCAN_CFG_PS1_BIT) & GRCAN_CFG_PS1;
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config |= (conf->timing.ps2<<GRCAN_CFG_PS2_BIT) & GRCAN_CFG_PS2;
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config |= (conf->timing.scaler<<GRCAN_CFG_SCALER_BIT) & GRCAN_CFG_SCALER;
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config |= (conf->timing.bpr << GRCAN_CFG_BPR_BIT) & GRCAN_CFG_BPR;
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config |= (conf->timing.rsj << GRCAN_CFG_RSJ_BIT) & GRCAN_CFG_RSJ;
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config |= (conf->timing.ps1 << GRCAN_CFG_PS1_BIT) & GRCAN_CFG_PS1;
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config |= (conf->timing.ps2 << GRCAN_CFG_PS2_BIT) & GRCAN_CFG_PS2;
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config |=
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(conf->timing.scaler << GRCAN_CFG_SCALER_BIT) & GRCAN_CFG_SCALER;
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/* Write configuration */
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regs->conf = config;
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@@ -518,7 +516,7 @@ static void grcan_hw_config(
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static void grcan_hw_accept(
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struct grcan_regs *regs,
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struct grcan_filter *afilter
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)
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)
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{
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/* Disable Sync mask totaly (if we change scode or smask
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* in an unfortunate way we may trigger a sync match)
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@@ -530,10 +528,7 @@ static void grcan_hw_accept(
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regs->rx0mask = afilter->mask;
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}
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static void grcan_hw_sync(
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struct grcan_regs *regs,
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struct grcan_filter *sfilter
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)
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static void grcan_hw_sync(struct grcan_regs *regs, struct grcan_filter *sfilter)
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{
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/* Disable Sync mask totaly (if we change scode or smask
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* in an unfortunate way we may trigger a sync match)
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@@ -547,21 +542,20 @@ static void grcan_hw_sync(
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static unsigned int grcan_hw_rxavail(
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unsigned int rp,
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unsigned int wp,
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unsigned int size
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)
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unsigned int wp, unsigned int size
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)
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{
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if ( rp == wp ) {
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if (rp == wp) {
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/* read pointer and write pointer is equal only
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* when RX buffer is empty.
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*/
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return 0;
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}
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if ( wp > rp ) {
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return (wp-rp)/GRCAN_MSG_SIZE;
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}else{
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return (size-(rp-wp))/GRCAN_MSG_SIZE;
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if (wp > rp) {
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return (wp - rp) / GRCAN_MSG_SIZE;
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} else {
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return (size - (rp - wp)) / GRCAN_MSG_SIZE;
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}
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}
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@@ -569,36 +563,36 @@ static unsigned int grcan_hw_txspace(
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unsigned int rp,
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unsigned int wp,
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unsigned int size
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)
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)
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{
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unsigned int left;
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if ( rp == wp ) {
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if (rp == wp) {
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/* read pointer and write pointer is equal only
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* when TX buffer is empty.
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*/
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return size/GRCAN_MSG_SIZE-WRAP_AROUND_TX_MSGS;
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return size / GRCAN_MSG_SIZE - WRAP_AROUND_TX_MSGS;
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}
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/* size - 4 - abs(read-write) */
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if ( wp > rp ) {
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left = size-(wp-rp);
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}else{
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left = rp-wp;
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if (wp > rp) {
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left = size - (wp - rp);
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} else {
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left = rp - wp;
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}
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return left/GRCAN_MSG_SIZE-WRAP_AROUND_TX_MSGS;
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return left / GRCAN_MSG_SIZE - WRAP_AROUND_TX_MSGS;
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}
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static int grcan_hw_rx_ongoing(struct grcan_regs *regs)
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{
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return READ_REG(®s->rx0ctrl) & GRCAN_RXCTRL_ONGOING;
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};
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}
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static int grcan_hw_tx_ongoing(struct grcan_regs *regs)
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{
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return READ_REG(®s->tx0ctrl) & GRCAN_TXCTRL_ONGOING;
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};
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}
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#define MIN_TSEG1 1
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@@ -611,20 +605,20 @@ static int grcan_calc_timing(
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unsigned int core_hz, /* Frequency in Hz of GRCAN Core */
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unsigned int sampl_pt,
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struct grcan_timing *timing /* result is placed here */
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)
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)
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{
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int best_error = 1000000000;
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int error;
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int best_tseg=0, best_brp=0, brp=0;
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int tseg=0, tseg1=0, tseg2=0;
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int best_tseg = 0, best_brp = 0, brp = 0;
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int tseg = 0, tseg1 = 0, tseg2 = 0;
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int sjw = 1;
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/* Default to 90% */
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if ( (sampl_pt < 50) || (sampl_pt>99) ){
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if ((sampl_pt < 50) || (sampl_pt > 99)) {
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sampl_pt = GRCAN_SAMPLING_POINT;
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}
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if ( (baud<5000) || (baud>1000000) ){
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if ((baud < 5000) || (baud > 1000000)) {
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/* invalid speed mode */
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return -1;
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}
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@@ -641,75 +635,71 @@ static int grcan_calc_timing(
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sampl_pt = 75;
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/* tseg even = round down, odd = round up */
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for (tseg = (MIN_TSEG1 + MIN_TSEG2 + 2) * 2;
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for (
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tseg = (MIN_TSEG1 + MIN_TSEG2 + 2) * 2;
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tseg <= (MAX_TSEG2 + MAX_TSEG1 + 2) * 2 + 1;
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tseg++)
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{
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tseg++
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) {
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brp = core_hz / ((1 + tseg / 2) * baud) + tseg % 2;
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if ((brp <= 0) ||
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( (brp > 256*1) && (brp <= 256*2) && (brp&0x1) ) ||
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( (brp > 256*2) && (brp <= 256*4) && (brp&0x3) ) ||
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( (brp > 256*4) && (brp <= 256*8) && (brp&0x7) ) ||
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(brp > 256*8)
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if (
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(brp <= 0) ||
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((brp > 256 * 1) && (brp <= 256 * 2) && (brp & 0x1)) ||
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((brp > 256 * 2) && (brp <= 256 * 4) && (brp & 0x3)) ||
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((brp > 256 * 4) && (brp <= 256 * 8) && (brp & 0x7)) ||
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(brp > 256 * 8)
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)
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continue;
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error = baud - core_hz / (brp * (1 + tseg / 2));
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if (error < 0)
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{
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if (error < 0) {
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error = -error;
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}
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if (error <= best_error)
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{
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if (error <= best_error) {
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best_error = error;
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best_tseg = tseg/2;
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best_brp = brp-1;
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best_tseg = tseg / 2;
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best_brp = brp - 1;
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}
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}
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if (best_error && (baud / best_error < 10))
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{
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if (best_error && (baud / best_error < 10)) {
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return -2;
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}else if ( !timing )
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} else if (!timing)
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return 0; /* nothing to store result in, but a valid bitrate can be calculated */
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tseg2 = best_tseg - (sampl_pt * (best_tseg + 1)) / 100;
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if (tseg2 < MIN_TSEG2)
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{
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if (tseg2 < MIN_TSEG2) {
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tseg2 = MIN_TSEG2;
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}
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if (tseg2 > MAX_TSEG2)
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{
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if (tseg2 > MAX_TSEG2) {
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tseg2 = MAX_TSEG2;
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}
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tseg1 = best_tseg - tseg2 - 2;
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if (tseg1 > MAX_TSEG1)
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{
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if (tseg1 > MAX_TSEG1) {
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tseg1 = MAX_TSEG1;
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tseg2 = best_tseg - tseg1 - 2;
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}
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/* Get scaler and BRP from pseudo BRP */
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if ( best_brp <= 256 ){
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if (best_brp <= 256) {
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timing->scaler = best_brp;
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timing->bpr = 0;
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}else if ( best_brp <= 256*2 ){
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timing->scaler = ((best_brp+1)>>1) -1;
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} else if (best_brp <= 256 * 2) {
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timing->scaler = ((best_brp + 1) >> 1) - 1;
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timing->bpr = 1;
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}else if ( best_brp <= 256*4 ){
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timing->scaler = ((best_brp+1)>>2) -1;
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} else if (best_brp <= 256 * 4) {
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timing->scaler = ((best_brp + 1) >> 2) - 1;
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timing->bpr = 2;
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}else{
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timing->scaler = ((best_brp+1)>>3) -1;
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} else {
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timing->scaler = ((best_brp + 1) >> 3) - 1;
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timing->bpr = 3;
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}
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timing->ps1 = tseg1+1;
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timing->ps1 = tseg1 + 1;
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timing->ps2 = tseg2;
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timing->rsj = sjw;
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@@ -719,14 +709,14 @@ static int grcan_calc_timing(
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static unsigned int grcan_hw_read_try(
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struct grcan_priv *pDev,
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struct grcan_regs *regs,
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CANMsg *buffer,
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CANMsg * buffer,
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int max
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)
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)
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{
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int i,j;
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int i, j;
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CANMsg *dest;
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struct grcan_msg *source,tmp;
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unsigned int wp,rp,size,rxmax,addr,trunk_msg_cnt;
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struct grcan_msg *source, tmp;
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unsigned int wp, rp, size, rxmax, addr, trunk_msg_cnt;
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FUNCDBG();
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@@ -740,48 +730,50 @@ static unsigned int grcan_hw_read_try(
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* reached the write pointer (empty buffer)
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*
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*/
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if ( wp != rp ){
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if (wp != rp) {
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/* Not empty, we have received chars...
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* Read as much as possible from DMA buffer
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*/
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size = READ_REG(®s->rx0size);
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/* Get number of bytes available in RX buffer */
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trunk_msg_cnt = grcan_hw_rxavail(rp,wp,size);
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trunk_msg_cnt = grcan_hw_rxavail(rp, wp, size);
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/* truncate size if user space buffer hasn't room for
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* all received chars.
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*/
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if ( trunk_msg_cnt > max )
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if (trunk_msg_cnt > max)
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trunk_msg_cnt = max;
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/* Read until i is 0 */
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i=trunk_msg_cnt;
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i = trunk_msg_cnt;
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addr = (unsigned int)pDev->rx;
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source = (struct grcan_msg *)(addr + rp);
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dest = buffer;
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rxmax = addr + (size-GRCAN_MSG_SIZE);
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rxmax = addr + (size - GRCAN_MSG_SIZE);
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/* Read as many can messages as possible */
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while(i>0){
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while (i > 0) {
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/* Read CAN message from DMA buffer */
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tmp.head[0] = READ_DMA_WORD(&source->head[0]);
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tmp.head[1] = READ_DMA_WORD(&source->head[1]);
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/* Convert one grcan CAN message to one "software" CAN message */
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dest->extended = tmp.head[0]>>31;
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dest->rtr = (tmp.head[0] >>30) & 0x1;
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if ( dest->extended ){
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dest->extended = tmp.head[0] >> 31;
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dest->rtr = (tmp.head[0] >> 30) & 0x1;
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if (dest->extended) {
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dest->id = tmp.head[0] & 0x3fffffff;
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}else{
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dest->id = (tmp.head[0] >>18) & 0xfff;
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} else {
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dest->id = (tmp.head[0] >> 18) & 0xfff;
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}
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dest->len = tmp.head[1] >> 28;
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for(j=0; j<dest->len; j++)
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for (j = 0; j < dest->len; j++)
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dest->data[j] = READ_DMA_BYTE(&source->data[j]);
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/* wrap around if neccessary */
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source = ( (unsigned int)source >= rxmax ) ? (struct grcan_msg *)addr : source+1;
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source =
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((unsigned int)source >= rxmax) ?
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(struct grcan_msg *)addr : source + 1;
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dest++; /* straight user buffer */
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i--;
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}
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@@ -789,11 +781,11 @@ static unsigned int grcan_hw_read_try(
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* ! wait for registers to be safely re-configurable
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*/
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regs->rx0ctrl = 0; /* DISABLE RX CHANNEL */
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i=0;
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while( grcan_hw_rx_ongoing(regs) && (i<1000) ){
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i = 0;
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while (grcan_hw_rx_ongoing(regs) && (i < 1000)) {
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i++;
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}
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regs->rx0rd = (unsigned int)source-addr;
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regs->rx0rd = (unsigned int)source - addr;
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regs->rx0ctrl = GRCAN_RXCTRL_ENABLE; /* ENABLE_RX_CHANNEL */
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return trunk_msg_cnt;
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}
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@@ -803,9 +795,9 @@ static unsigned int grcan_hw_read_try(
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static unsigned int grcan_hw_write_try(
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struct grcan_priv *pDev,
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struct grcan_regs *regs,
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CANMsg *buffer,
|
||||
CANMsg * buffer,
|
||||
int count
|
||||
)
|
||||
)
|
||||
{
|
||||
unsigned int rp, wp, size, txmax, addr, ret;
|
||||
struct grcan_msg *dest;
|
||||
@@ -814,45 +806,47 @@ static unsigned int grcan_hw_write_try(
|
||||
unsigned int tmp;
|
||||
int i;
|
||||
|
||||
DBGC(DBG_TX,"\n");
|
||||
/*FUNCDBG();*/
|
||||
DBGC(DBG_TX, "\n");
|
||||
/*FUNCDBG(); */
|
||||
|
||||
rp = READ_REG(®s->tx0rd);
|
||||
wp = READ_REG(®s->tx0wr);
|
||||
size = READ_REG(®s->tx0size);
|
||||
|
||||
space_left = grcan_hw_txspace(rp,wp,size);
|
||||
space_left = grcan_hw_txspace(rp, wp, size);
|
||||
|
||||
/* is circular fifo full? */
|
||||
if ( space_left < 1 )
|
||||
if (space_left < 1)
|
||||
return 0;
|
||||
|
||||
/* Truncate size */
|
||||
if ( space_left > count )
|
||||
if (space_left > count)
|
||||
space_left = count;
|
||||
ret = space_left;
|
||||
|
||||
addr = (unsigned int)pDev->tx;
|
||||
|
||||
dest = (struct grcan_msg *)(addr + wp);
|
||||
source = (CANMsg *)buffer;
|
||||
txmax = addr + (size-GRCAN_MSG_SIZE);
|
||||
source = (CANMsg *) buffer;
|
||||
txmax = addr + (size - GRCAN_MSG_SIZE);
|
||||
|
||||
while ( space_left>0 ) {
|
||||
while (space_left > 0) {
|
||||
/* Convert and write CAN message to DMA buffer */
|
||||
if ( source->extended ){
|
||||
tmp = (1<<31) | (source->id & 0x3fffffff);
|
||||
}else{
|
||||
tmp = (source->id&0xfff)<<18;
|
||||
if (source->extended) {
|
||||
tmp = (1 << 31) | (source->id & 0x3fffffff);
|
||||
} else {
|
||||
tmp = (source->id & 0xfff) << 18;
|
||||
}
|
||||
if ( source->rtr )
|
||||
tmp|=(1<<30);
|
||||
if (source->rtr)
|
||||
tmp |= (1 << 30);
|
||||
dest->head[0] = tmp;
|
||||
dest->head[1] = source->len<<28;
|
||||
for ( i=0; i<source->len; i++)
|
||||
dest->head[1] = source->len << 28;
|
||||
for (i = 0; i < source->len; i++)
|
||||
dest->data[i] = source->data[i];
|
||||
source++; /* straight user buffer */
|
||||
dest = ((unsigned int)dest >= txmax) ? (struct grcan_msg *)addr : dest+1;
|
||||
dest =
|
||||
((unsigned int)dest >= txmax) ?
|
||||
(struct grcan_msg *)addr : dest + 1;
|
||||
space_left--;
|
||||
}
|
||||
|
||||
@@ -860,8 +854,8 @@ static unsigned int grcan_hw_write_try(
|
||||
* ! wait for registers to be safely re-configurable
|
||||
*/
|
||||
regs->tx0ctrl = 0; /* DISABLE TX CHANNEL */
|
||||
i=0;
|
||||
while( (grcan_hw_tx_ongoing(regs)) && i<1000 ){
|
||||
i = 0;
|
||||
while ((grcan_hw_tx_ongoing(regs)) && i < 1000) {
|
||||
i++;
|
||||
}
|
||||
regs->tx0wr = (unsigned int)dest - addr; /* Update write pointer */
|
||||
@@ -869,10 +863,7 @@ static unsigned int grcan_hw_write_try(
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int grcan_wait_rxdata(
|
||||
struct grcan_priv *pDev,
|
||||
int min
|
||||
)
|
||||
static int grcan_wait_rxdata(struct grcan_priv *pDev, int min)
|
||||
{
|
||||
unsigned int wp, rp, size, irq;
|
||||
unsigned int irq_trunk, dataavail;
|
||||
@@ -892,11 +883,11 @@ static int grcan_wait_rxdata(
|
||||
wp = READ_REG(&pDev->regs->rx0wr);
|
||||
|
||||
/**** Calculate IRQ Pointer ****/
|
||||
irq = wp + min*GRCAN_MSG_SIZE;
|
||||
irq = wp + min * GRCAN_MSG_SIZE;
|
||||
/* wrap irq around */
|
||||
if ( irq >= size ){
|
||||
irq_trunk = irq-size;
|
||||
}else
|
||||
if (irq >= size) {
|
||||
irq_trunk = irq - size;
|
||||
} else
|
||||
irq_trunk = irq;
|
||||
|
||||
/* init IRQ HW */
|
||||
@@ -908,21 +899,27 @@ static int grcan_wait_rxdata(
|
||||
wp = READ_REG(&pDev->regs->rx0wr);
|
||||
|
||||
/* Calculate messages available */
|
||||
dataavail = grcan_hw_rxavail(rp,wp,size);
|
||||
dataavail = grcan_hw_rxavail(rp, wp, size);
|
||||
|
||||
if ( dataavail < min ){
|
||||
if (dataavail < min) {
|
||||
/* Still empty, proceed with sleep - Turn on IRQ (unmask irq) */
|
||||
pDev->regs->imr = READ_REG(&pDev->regs->imr) | GRCAN_RXIRQ_IRQ;
|
||||
wait=1;
|
||||
}else{
|
||||
wait = 1;
|
||||
} else {
|
||||
/* enough message has been received, abort sleep - don't unmask interrupt */
|
||||
wait=0;
|
||||
wait = 0;
|
||||
}
|
||||
IRQ_GLOBAL_ENABLE(oldLevel);
|
||||
|
||||
/* Wait for IRQ to fire only if has been triggered */
|
||||
if ( wait ){
|
||||
if ( rtems_semaphore_obtain(pDev->rx_sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT) == RTEMS_UNSATISFIED )
|
||||
if (wait) {
|
||||
if (
|
||||
rtems_semaphore_obtain(
|
||||
pDev->rx_sem,
|
||||
RTEMS_WAIT,
|
||||
RTEMS_NO_TIMEOUT
|
||||
) == RTEMS_UNSATISFIED
|
||||
)
|
||||
return -1; /* Device driver has been closed or stopped, return with error status */
|
||||
}
|
||||
|
||||
@@ -936,18 +933,15 @@ static int grcan_wait_rxdata(
|
||||
* than max buffer for this algo to work.
|
||||
*
|
||||
*/
|
||||
static int grcan_wait_txspace(
|
||||
struct grcan_priv *pDev,
|
||||
int min
|
||||
)
|
||||
static int grcan_wait_txspace(struct grcan_priv *pDev, int min)
|
||||
{
|
||||
int wait;
|
||||
unsigned int irq, rp, wp, size, space_left;
|
||||
unsigned int irq_trunk;
|
||||
IRQ_GLOBAL_PREPARE(oldLevel);
|
||||
|
||||
DBGC(DBG_TX,"\n");
|
||||
/*FUNCDBG();*/
|
||||
DBGC(DBG_TX, "\n");
|
||||
/*FUNCDBG(); */
|
||||
|
||||
IRQ_GLOBAL_DISABLE(oldLevel);
|
||||
|
||||
@@ -959,11 +953,11 @@ static int grcan_wait_txspace(
|
||||
rp = READ_REG(&pDev->regs->tx0rd);
|
||||
|
||||
/**** Calculate IRQ Pointer ****/
|
||||
irq = rp + min*GRCAN_MSG_SIZE;
|
||||
irq = rp + min * GRCAN_MSG_SIZE;
|
||||
/* wrap irq around */
|
||||
if ( irq >= size ){
|
||||
if (irq >= size) {
|
||||
irq_trunk = irq - size;
|
||||
}else
|
||||
} else
|
||||
irq_trunk = irq;
|
||||
|
||||
/* trigger HW to do a IRQ when enough room in buffer */
|
||||
@@ -981,22 +975,22 @@ static int grcan_wait_txspace(
|
||||
*/
|
||||
rp = READ_REG(&pDev->regs->tx0rd);
|
||||
|
||||
space_left = grcan_hw_txspace(rp,wp,size);
|
||||
space_left = grcan_hw_txspace(rp, wp, size);
|
||||
|
||||
if ( space_left < min ){
|
||||
if (space_left < min) {
|
||||
/* Still too full, proceed with sleep - Turn on IRQ (unmask irq) */
|
||||
pDev->regs->imr = READ_REG(&pDev->regs->imr) | GRCAN_TXIRQ_IRQ;
|
||||
wait=1;
|
||||
}else{
|
||||
wait = 1;
|
||||
} else {
|
||||
/* There are enough room in buffer, abort wait - don't unmask interrupt */
|
||||
wait=0;
|
||||
wait = 0;
|
||||
}
|
||||
IRQ_GLOBAL_ENABLE(oldLevel);
|
||||
|
||||
/* Wait for IRQ to fire only if it has been triggered */
|
||||
if ( wait ){
|
||||
if ( rtems_semaphore_obtain(pDev->tx_sem, RTEMS_WAIT, 100) ==
|
||||
RTEMS_UNSATISFIED ){
|
||||
if (wait) {
|
||||
if (rtems_semaphore_obtain(pDev->tx_sem, RTEMS_WAIT, 100) ==
|
||||
RTEMS_UNSATISFIED) {
|
||||
/* Device driver has flushed us, this may be due to another thread has
|
||||
* closed the device, this is to avoid deadlock */
|
||||
return -1;
|
||||
@@ -1019,27 +1013,32 @@ static int grcan_tx_flush(struct grcan_priv *pDev)
|
||||
*
|
||||
* Hardware doesn't update write pointer - we do
|
||||
*/
|
||||
while ( (wp=READ_REG(&pDev->regs->tx0wr)) != (rp=READ_REG(&pDev->regs->tx0rd)) ) {
|
||||
while (
|
||||
(wp = READ_REG(&pDev->regs->tx0wr)) !=
|
||||
(rp = READ_REG(&pDev->regs->tx0rd))
|
||||
) {
|
||||
/* Wait for TX empty IRQ */
|
||||
IRQ_GLOBAL_DISABLE(oldLevel);
|
||||
/* Clear pending TXEmpty IRQ */
|
||||
pDev->regs->picr = GRCAN_TXEMPTY_IRQ;
|
||||
|
||||
if ( wp != READ_REG(&pDev->regs->tx0rd) ) {
|
||||
if (wp != READ_REG(&pDev->regs->tx0rd)) {
|
||||
/* Still not empty, proceed with sleep - Turn on IRQ (unmask irq) */
|
||||
pDev->regs->imr = READ_REG(&pDev->regs->imr) | GRCAN_TXEMPTY_IRQ;
|
||||
pDev->regs->imr =
|
||||
READ_REG(&pDev->regs->imr) | GRCAN_TXEMPTY_IRQ;
|
||||
wait = 1;
|
||||
}else{
|
||||
} else {
|
||||
/* TX fifo is empty */
|
||||
wait = 0;
|
||||
}
|
||||
IRQ_GLOBAL_ENABLE(oldLevel);
|
||||
if ( !wait )
|
||||
if (!wait)
|
||||
break;
|
||||
|
||||
/* Wait for IRQ to wake us */
|
||||
if ( rtems_semaphore_obtain(pDev->txempty_sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT) ==
|
||||
RTEMS_UNSATISFIED ) {
|
||||
if (rtems_semaphore_obtain
|
||||
(pDev->txempty_sem, RTEMS_WAIT,
|
||||
RTEMS_NO_TIMEOUT) == RTEMS_UNSATISFIED) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
@@ -1145,13 +1144,13 @@ static void grcan_free_buffers(struct grcan_priv *pDev, int rx, int tx)
|
||||
{
|
||||
FUNCDBG();
|
||||
|
||||
if ( tx && pDev->_tx ){
|
||||
if (tx && pDev->_tx) {
|
||||
free(pDev->_tx);
|
||||
pDev->_tx = NULL;
|
||||
pDev->tx = NULL;
|
||||
}
|
||||
|
||||
if ( rx && pDev->_rx ){
|
||||
if (rx && pDev->_rx) {
|
||||
free(pDev->_rx);
|
||||
pDev->_rx = NULL;
|
||||
pDev->rx = NULL;
|
||||
@@ -1306,11 +1305,10 @@ int grcan_read(void *d, CANMsg *msg, size_t ucount)
|
||||
}
|
||||
}
|
||||
|
||||
while(count == 0 || (pDev->rxcomplete && (count!=req_cnt)) ){
|
||||
|
||||
if ( !pDev->rxcomplete ){
|
||||
while (count == 0 || (pDev->rxcomplete && (count!=req_cnt))) {
|
||||
if (!pDev->rxcomplete) {
|
||||
left = 1; /* return as soon as there is one message available */
|
||||
}else{
|
||||
} else {
|
||||
left = req_cnt - count; /* return as soon as all data are available */
|
||||
|
||||
/* never wait for more than the half the maximum size of the receive buffer
|
||||
@@ -1318,12 +1316,12 @@ int grcan_read(void *d, CANMsg *msg, size_t ucount)
|
||||
* otherwise we would have to copy everything when the data has been
|
||||
* received.
|
||||
*/
|
||||
if ( left > ((pDev->rxbuf_size/GRCAN_MSG_SIZE)/2) ){
|
||||
left = (pDev->rxbuf_size/GRCAN_MSG_SIZE)/2;
|
||||
if (left > ((pDev->rxbuf_size/GRCAN_MSG_SIZE) / 2)){
|
||||
left = (pDev->rxbuf_size/GRCAN_MSG_SIZE) / 2;
|
||||
}
|
||||
}
|
||||
|
||||
if ( grcan_wait_rxdata(pDev,left) ) {
|
||||
if (grcan_wait_rxdata(pDev, left)) {
|
||||
/* The wait has been aborted, probably due to
|
||||
* the device driver has been closed by another
|
||||
* thread.
|
||||
|
||||
Reference in New Issue
Block a user