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2001-11-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>

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* custom/dmv177.cfg: Reflect changes to dmv177/configure.ac.
	* custom/ppcn_60x.cfg: Refect changes to ppcn_60x/configure.ac.
	* custom/psim.cfg: Refect changes to psim/configure.ac.
	* custom/score603e.cfg: Reflect changes to score603e/configure.ac,
	remove SCORE603E_GENERATION.
This commit is contained in:
Joel Sherrill
2001-11-21 18:35:42 +00:00
parent 65c34da02b
commit bbb6af24fa
5 changed files with 10 additions and 137 deletions
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8
make/ChangeLog
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@@ -1,4 +1,12 @@
2001-11-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* custom/dmv177.cfg: Reflect changes to dmv177/configure.ac.
* custom/ppcn_60x.cfg: Refect changes to ppcn_60x/configure.ac.
* custom/psim.cfg: Refect changes to psim/configure.ac.
* custom/score603e.cfg: Reflect changes to score603e/configure.ac,
remove SCORE603E_GENERATION.
2001-11-16 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* custom/eth_comm.cfg: Reflect changes to eth_comm/configure.ac.

33
make/custom/dmv177.cfg
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@@ -16,39 +16,6 @@ RTEMS_CPU_MODEL=ppc603e
# This is the actual bsp directory used during the build process.
RTEMS_BSP_FAMILY=dmv177
# This section makes the target dependent options file.
# PPC_VECTOR_FILE_BASE (ppc)
# This defines the base address of the exception table.
# NOTE: Vectors are actually at 0xFFF00000 but file starts at offset 0x0100
#
# PPC_USE_SPRG (RTEMS PowerPC port)
# If defined, then the PowerPC specific code in RTEMS will use some
# of the special purpose registers to slightly optimize interrupt
# response time. The use of these registers can conflict with
# other tools like debuggers.
#
# PPC_USE_DATA_CACHE (RTEMS PowerPC port/BSP)
# If defined, then the PowerPC specific code in RTEMS will use
# data cache instructions to optimize the context switch code.
# This code can conflict with debuggers or emulators. It is known
# to break the Corelis PowerPC emulator with at least some combinations
# of PowerPC 603e revisions and emulator versions.
# The BSP actually contains the call that enables this.
#
# PPC_USE_INSTRUCTION_CACHE (RTEMS PowerPC port/BSP)
# If defined, then the PowerPC specific code in RTEMS will use
# data cache instructions to optimize the context switch code.
# This code can conflict with debuggers or emulators.
# The BSP actually contains the call that enables this.
define make-target-options
@echo "#define PPC_VECTOR_FILE_BASE 0x0100" >>$@
@echo "#define PPC_USE_SPRG 0" >>$@
@echo "#define PPC_USE_DATA_CACHE 0" >>$@
@echo "#define PPC_USE_INSTRUCTION_CACHE 1" >>$@
endef
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
#

33
make/custom/ppcn_60x.cfg
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@@ -13,39 +13,6 @@ RTEMS_CPU_MODEL=ppc603e
RTEMS_BSP_FAMILY=ppcn_60x
# This contains the compiler options necessary to select the CPU model
# This section makes the target dependent options file.
# PPCN_60X_USE_DINK (ppcn_60x_bsp)
# PPCN_60X_USE_NONE (ppcn_60x_bsp)
# The Score603e board can be configured with 3 ROM monitors. Only two
# are appropriate for use with RTEMS. Set exactly one of these to "1"
# to indicate which ROM monitor is on the board you are using.
#
# PPC_VECTOR_FILE_BASE (ppc)
# This defines the base address of the exception table.
# NOTE: Vectors are actually at 0xFFF00000 but file starts at offset 0x0100
#
# PPC_USE_SPRG (RTEMS PowerPC port)
# If defined, then the PowerPC specific code in RTEMS will use some
# of the special purpose registers to slightly optimize interrupt
# response time. The use of these registers can conflict with
# other tools like debuggers.
#
# PPC_USE_DATA_CACHE (RTEMS PowerPC port)
# If defined, then the PowerPC specific code in RTEMS will use
# data cache instructions to optimize the context switch code.
# This code can conflict with debuggers or emulators.
#
define make-target-options
@echo "#define PPCN_60X_USE_DINK 1" >>$@
@echo "#define PPCN_60X_USE_NONE 0" >>$@
@echo "#define PPC_USE_DATA_CACHE 1" >>$@
@echo "#define PPC_VECTOR_FILE_BASE 0x0100" >>$@
@echo "#define PPC_USE_SPRG 0" >>$@
endef
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
#

17
make/custom/psim.cfg
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@@ -12,23 +12,6 @@ RTEMS_CPU_MODEL=ppc603e
# This is the actual bsp directory used during the build process.
RTEMS_BSP_FAMILY=psim
# This section makes the target dependent options file.
# PPC_VECTOR_FILE_BASE (PowerPC)
# This defines the base address of the exception table.
# NOTE: Vectors are actually at 0xFFF00000 but file starts at offset 0x0100
#
# PPC_USE_SPRG (RTEMS PowerPC port)
# If defined, then the PowerPC specific code in RTEMS will use some
# of the special purpose registers to slightly optimize interrupt
# response time. The use of these registers can conflict with
# other tools like debuggers.
define make-target-options
@echo "#define PPC_VECTOR_FILE_BASE 0xFFF00100" >>$@
@echo "#define PPC_USE_SPRG 1" >>$@
endef
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
#

56
make/custom/score603e.cfg
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@@ -7,67 +7,15 @@
# $Id$
#
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU=powerpc
RTEMS_CPU_MODEL=ppc603e
# Set the default generation if it has not been overridden
ifeq ($(SCORE603E_GENERATION),)
SCORE603E_GENERATION=2
endif
# This is the actual bsp directory used during the build process.
RTEMS_BSP_FAMILY=score603e
ifeq ($(SCORE603E_GENERATION),1)
RTEMS_BSP=score603e_g1
else
ifeq ($(SCORE603E_GENERATION),2)
RTEMS_BSP=score603e
endif # generation 2
endif # generation 1
include $(RTEMS_ROOT)/make/custom/default.cfg
# This section makes the target dependent options file.
# SCORE603E_USE_SDS (score603e_bsp)
# SCORE603E_USE_OPEN_FIRMWARE (score603e_bsp)
# SCORE603E_USE_NONE (score603e_bsp)
# The Score603e board can be configured with 3 ROM monitors. Only two
# are appropriate for use with RTEMS. Set exactly one of these to "1"
# to indicate which ROM monitor is on the board you are using.
#
# PPC_VECTOR_FILE_BASE (ppc)
# This defines the base address of the exception table.
# NOTE: Vectors are actually at 0xFFF00000 but file starts at offset 0x0100
#
# PPC_USE_SPRG (RTEMS PowerPC port)
# If defined, then the PowerPC specific code in RTEMS will use some
# of the special purpose registers to slightly optimize interrupt
# response time. The use of these registers can conflict with
# other tools like debuggers.
#
# PPC_USE_DATA_CACHE (RTEMS PowerPC port)
# If defined, then the PowerPC specific code in RTEMS will use
# data cache instructions to optimize the context switch code.
# This code can conflict with debuggers or emulators.
#
define make-target-options
@echo "#define INITIALIZE_COM_PORTS 1" >>$@
@echo "#define SCORE603E_GENERATION $(SCORE603E_GENERATION)" >>$@
@echo "#define SCORE603E_USE_SDS 0" >>$@
@echo "#define SCORE603E_USE_NONE 0" >>$@
@echo "#define SCORE603E_USE_DINK 1" >>$@
@echo "#define SCORE603E_USE_OPEN_FIRMWARE 0" >>$@
@echo "#define PPC_USE_DATA_CACHE 0" >>$@
@echo "#define PPC_VECTOR_FILE_BASE 0x0100" >>$@
@echo "#define PPC_USE_SPRG 0" >>$@
@echo "#define HAS_PMC_PSC8 0" >>$@
endef
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.