RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

bsps/riscv: Always dispatch software interrupts

Browse Source 
This helps to run the interrupt API validation tests.
This commit is contained in:
Sebastian Huber
2022-11-09 14:46:44 +01:00
parent 47d156d706
commit ba53a177ab
1 changed files with 2 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
bsps/riscv/riscv/irq/irq.c
View File

@@ -99,7 +99,6 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
__asm__ volatile ("fence o, i" : : : "memory");
}
} else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) {
#ifdef RTEMS_SMP
/*
* Clear the software interrupt on this processor. Synchronization of
* inter-processor interrupts is done via Per_CPU_Control::message in
@@ -107,10 +106,10 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
*/
*cpu_self->cpu_per_cpu.clint_msip = 0;
#ifdef RTEMS_SMP
_SMP_Inter_processor_interrupt_handler(cpu_self);
#else
bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE);
#endif
bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE);
} else {
bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION);
}