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bsps/riscv: Always dispatch software interrupts

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This helps to run the interrupt API validation tests.
This commit is contained in:
Sebastian Huber
2022-11-09 14:46:44 +01:00
parent 47d156d706
commit ba53a177ab
1 changed files with 2 additions and 3 deletions
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5
bsps/riscv/riscv/irq/irq.c
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@@ -99,7 +99,6 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
__asm__ volatile ("fence o, i" : : : "memory"); __asm__ volatile ("fence o, i" : : : "memory");
} }
} else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) { } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) {
#ifdef RTEMS_SMP
/* /*
* Clear the software interrupt on this processor. Synchronization of * Clear the software interrupt on this processor. Synchronization of
* inter-processor interrupts is done via Per_CPU_Control::message in * inter-processor interrupts is done via Per_CPU_Control::message in
@@ -107,10 +106,10 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
*/ */
*cpu_self->cpu_per_cpu.clint_msip = 0; *cpu_self->cpu_per_cpu.clint_msip = 0;
#ifdef RTEMS_SMP
_SMP_Inter_processor_interrupt_handler(cpu_self); _SMP_Inter_processor_interrupt_handler(cpu_self);
#else
bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE);
#endif #endif
bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE);
} else { } else {
bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION); bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION);
} }