RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

2001-04-20 Joel Sherrill <joel@OARcorp.com>

Browse Source 
* mongoosev/duart/mg5uart.c (mg5uart_enable_interrupts): Honor
	the other bits set in the Peripheral Function Interrupt Mask
	Register when modifying those enabled for the DUART.
	* mongoosev/include/mongoose-v.h (MONGOOSEV_ATOMIC_MASK,
	MONGOOSEV_PFICR, MONGOOSEV_PFIMR, mongoosev_set_in_pficr,
	mongoosev_clear_in_pficr, mongoosev_set_in_pfimr,
	mongoosev_clear_in_pfimr, MONGOOSEV_UART_ALL_IRQ_BITS): New macros.
This commit is contained in:
Joel Sherrill
2001-04-20 13:24:39 +00:00
parent b335c50311
commit b85df3491f
3 changed files with 51 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
c/src/lib/libcpu/mips/ChangeLog
View File

@@ -1,3 +1,13 @@
2001-04-20 Joel Sherrill <joel@OARcorp.com>
* mongoosev/duart/mg5uart.c (mg5uart_enable_interrupts): Honor
the other bits set in the Peripheral Function Interrupt Mask
Register when modifying those enabled for the DUART.
* mongoosev/include/mongoose-v.h (MONGOOSEV_ATOMIC_MASK,
MONGOOSEV_PFICR, MONGOOSEV_PFIMR, mongoosev_set_in_pficr,
mongoosev_clear_in_pficr, mongoosev_set_in_pfimr,
mongoosev_clear_in_pfimr, MONGOOSEV_UART_ALL_IRQ_BITS): New macros.
2001-04-16 Joel Sherrill <joel@OARcorp.com>
* mongoosev/duart/mg5uart.c, mongoosev/duart/mg5uart.h

25
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c
View File

@@ -728,7 +728,8 @@ MG5UART_STATIC void mg5uart_enable_interrupts(
)
{
unsigned32 pMG5UART;
unsigned int shift;
unsigned32 shifted_mask;
unsigned32 shifted_bits;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
@@ -736,15 +737,21 @@ MG5UART_STATIC void mg5uart_enable_interrupts(
* Enable interrupts on RX and TX -- not break
*/
if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
shifted_bits = MONGOOSEV_UART_ALL_IRQ_BITS;
shifted_mask = mask;
MG5UART_SETREG(
pMG5UART,
MG5UART_INTERRUPT_MASK_REGISTER,
mask << shift
if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 ) {
shifted_bits <<= MONGOOSEV_UART0_IRQ_SHIFT;
shifted_mask <<= MONGOOSEV_UART0_IRQ_SHIFT;
} else {
shifted_bits <<= MONGOOSEV_UART1_IRQ_SHIFT;
shifted_mask <<= MONGOOSEV_UART1_IRQ_SHIFT;
}
MONGOOSEV_ATOMIC_MASK(
MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER,
shifted_bits,
shifted_mask
);
}

25
c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
View File

@@ -30,6 +30,17 @@
#define MONGOOSEV_WRITE_REGISTER( _base, _register, _value ) \
*((volatile unsigned32 *)((_base) + (_register))) = (_value)
#define MONGOOSEV_ATOMIC_MASK( _addr, _mask, _new ) \
do { \
rtems_interrupt_level Irql; \
rtems_unsigned32 tmp; \
\
rtems_interrupt_disable(Irql); \
tmp = *((volatile unsigned32 *)(_addr)) & ~(_mask); \
*((volatile unsigned32 *)(_addr)) = tmp | (_new); \
rtems_interrupt_enable(Irql); \
} while (0)
/*
* BIU and DRAM Registers
*/
@@ -50,6 +61,19 @@
#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER 0xFFFE0188
#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER 0xFFFE018C
#define MONGOOSEV_PFICR MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER
#define MONGOOSEV_PFIMR MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER
#define mongoosev_set_in_pficr( _mask, _bits ) \
MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFICR, _mask, _bits )
#define mongoosev_clear_in_pficr( _mask, _bits ) \
MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFICR, _mask, ~(_bits) )
#define mongoosev_set_in_pfimr( _mask, _bits ) \
MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFIMR, _mask, _bits )
#define mongoosev_clear_in_pfimr( _mask, _bits ) \
MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFIMR, _mask, ~(_bits) )
/* UART Bits in Peripheral Command Register Bits (TX/RX tied together here) */
#define MONGOOSEV_UART_CMD_RESET_BOTH_PORTS 0x0001
#define MONGOOSEV_UART_CMD_LOOPBACK_CTSN 0x0002
@@ -107,6 +131,7 @@
#define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x0003
#define MONGOOSEV_UART_ALL_STATUS_BITS 0x001F
#define MONGOOSEV_UART_ALL_IRQ_BITS 0x001F
/*
* The Peripheral Interrupt Status, Cause, and Mask registers have the