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2007-12-03 Joel Sherrill <joel.sherrill@oarcorp.com>

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* irq/irq.c: Spacing.
This commit is contained in:
Joel Sherrill
2007-12-03 22:36:08 +00:00
parent 12eebb497a
commit b75378abe7
2 changed files with 364 additions and 489 deletions
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4
c/src/lib/libbsp/powerpc/gen5200/ChangeLog
View File

@@ -1,3 +1,7 @@
2007-12-03 Joel Sherrill <joel.sherrill@oarcorp.com>
* irq/irq.c: Spacing.
2007-12-03 Joel Sherrill <joel.sherrill@OARcorp.com>
* startup/bspstart.c: Moved most of the remaining CPU Table fields to

439
c/src/lib/libbsp/powerpc/gen5200/irq/irq.c
View File

@@ -123,8 +123,8 @@ const static unsigned int SIU_MaskBit[BSP_SIU_IRQ_NUMBER] =
static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
{
return (((int)irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & ((int)irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET));
return (((int)irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
((int)irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET));
}
/*
@@ -133,7 +133,8 @@ static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
static inline int is_siu_irq(const rtems_irq_symbolic_name irqLine)
{
return (((int)irqLine <= BSP_SIU_IRQ_MAX_OFFSET) && ((int)irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET));
return (((int)irqLine <= BSP_SIU_IRQ_MAX_OFFSET) &&
((int)irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET));
}
@@ -146,19 +147,19 @@ static inline int get_siu_irq_base_index(const rtems_irq_symbolic_name irqLine)
if (irqLine <= BSP_PER_IRQ_MAX_OFFSET)
return BSP_PER_IRQ_LOWEST_OFFSET;
else
if (irqLine <= BSP_MAIN_IRQ_MAX_OFFSET)
return BSP_MAIN_IRQ_LOWEST_OFFSET;
else
if (irqLine <= BSP_CRIT_IRQ_MAX_OFFSET)
return BSP_CRIT_IRQ_LOWEST_OFFSET;
else
return -1;
return -1;
}
static inline void BSP_enable_per_irq_at_siu(const rtems_irq_symbolic_name irqLine)
static inline void BSP_enable_per_irq_at_siu(
const rtems_irq_symbolic_name irqLine
)
{
uint8_t lo_hi_ind = 0, prio_index_offset;
uint32_t *reg;
@@ -169,8 +170,7 @@ static inline void BSP_enable_per_irq_at_siu(const rtems_irq_symbolic_name irqLi
prio_index_offset = (irqLine - BSP_PER_IRQ_LOWEST_OFFSET) % 8;
/* set interrupt priorities */
if(irqPrioTable[irqLine] <= 15)
{
if (irqPrioTable[irqLine] <= 15) {
/* set peripheral int priority */
reg = (uint32_t *)(&(mpc5200.per_pri_1));
@@ -182,8 +182,7 @@ static inline void BSP_enable_per_irq_at_siu(const rtems_irq_symbolic_name irqLi
*reg |= (irqPrioTable[irqLine] << (28 - (prio_index_offset<< 2)));
/* test msb (hash-bit) and set LO_/HI_int indicator */
if((lo_hi_ind = (irqPrioTable[irqLine] >> 3)))
{
if ((lo_hi_ind = (irqPrioTable[irqLine] >> 3))) {
/* set critical HI_int priority */
reg = (uint32_t *)(&(mpc5200.crit_pri_main_mask));
@@ -196,29 +195,19 @@ static inline void BSP_enable_per_irq_at_siu(const rtems_irq_symbolic_name irqLi
*/
mpc5200.ext_en_type |= 1;
}
else
{
if(irqPrioTable[irqLine] <= 15)
{
} else {
if (irqPrioTable[irqLine] <= 15) {
/* set main LO_int priority */
reg = (uint32_t *)(&(mpc5200.main_pri_1));
*reg |= (irqPrioTable[BSP_SIU_IRQ_LO_INT] << 16);
}
}
}
/* if LO_int ind., enable (unmask) main interrupt */
if(!lo_hi_ind)
{
mpc5200.crit_pri_main_mask &= ~(0x80000000 >> SIU_MaskBit[BSP_SIU_IRQ_LO_INT]);
if (!lo_hi_ind) {
mpc5200.crit_pri_main_mask &=
~(0x80000000 >> SIU_MaskBit[BSP_SIU_IRQ_LO_INT]);
}
@@ -234,7 +223,9 @@ static inline void BSP_enable_per_irq_at_siu(const rtems_irq_symbolic_name irqLi
}
static inline void BSP_enable_main_irq_at_siu(const rtems_irq_symbolic_name irqLine)
static inline void BSP_enable_main_irq_at_siu(
const rtems_irq_symbolic_name irqLine
)
{
uint8_t prio_index_offset;
@@ -245,8 +236,7 @@ static inline void BSP_enable_main_irq_at_siu(const rtems_irq_symbolic_name irqL
prio_index_offset = (irqLine - BSP_MAIN_IRQ_LOWEST_OFFSET) % 8;
/* set main interrupt priority */
if(irqPrioTable[irqLine] <= 15)
{
if (irqPrioTable[irqLine] <= 15) {
/* set main int priority */
reg = (uint32_t *)(&(mpc5200.main_pri_1));
@@ -257,14 +247,10 @@ static inline void BSP_enable_main_irq_at_siu(const rtems_irq_symbolic_name irqL
/* set priority as given in priority table */
*reg |= (irqPrioTable[irqLine] << (28 - (prio_index_offset << 2)));
if((irqLine >= BSP_SIU_IRQ_IRQ1) && (irqLine <= BSP_SIU_IRQ_IRQ3))
{
if ((irqLine >= BSP_SIU_IRQ_IRQ1) && (irqLine <= BSP_SIU_IRQ_IRQ3)) {
/* enable external irq-pin */
mpc5200.ext_en_type |= (0x80000000 >> (20 + prio_index_offset));
}
}
/* enable (unmask) main interrupt */
@@ -273,9 +259,10 @@ static inline void BSP_enable_main_irq_at_siu(const rtems_irq_symbolic_name irqL
}
static inline void BSP_enable_crit_irq_at_siu(const rtems_irq_symbolic_name irqLine)
static inline void BSP_enable_crit_irq_at_siu(
const rtems_irq_symbolic_name irqLine
)
{
uint8_t prio_index_offset;
uint32_t *reg;
rtems_irq_prio *irqPrioTable = internal_config->irqPrioTbl;
@@ -291,8 +278,7 @@ static inline void BSP_enable_crit_irq_at_siu(const rtems_irq_symbolic_name irqL
/* set critical interrupt priorities */
if(irqPrioTable[irqLine] <= 3)
{
if (irqPrioTable[irqLine] <= 3) {
/* choose proper register */
reg = (uint32_t *)(&(mpc5200.crit_pri_main_mask));
@@ -301,22 +287,18 @@ static inline void BSP_enable_crit_irq_at_siu(const rtems_irq_symbolic_name irqL
*reg |= (irqPrioTable[irqLine] << (30 - (prio_index_offset << 1)));
/* external irq0-pin */
if(irqLine == BSP_SIU_IRQ_IRQ1)
{
if (irqLine == BSP_SIU_IRQ_IRQ1) {
/* enable external irq-pin */
mpc5200.ext_en_type |= (0x80000000 >> (20 + prio_index_offset));
}
}
}
static inline void BSP_disable_per_irq_at_siu(const rtems_irq_symbolic_name irqLine)
static inline void BSP_disable_per_irq_at_siu(
const rtems_irq_symbolic_name irqLine
)
{
uint8_t prio_index_offset;
uint32_t *reg;
@@ -330,13 +312,13 @@ static inline void BSP_disable_per_irq_at_siu(const rtems_irq_symbolic_name irqL
reg = (uint32_t *)(&(mpc5200.per_pri_1));
reg += (irqLine >> 3);
*reg &= ~(15 << (28 - (prio_index_offset << 2)));
}
static inline void BSP_disable_main_irq_at_siu(const rtems_irq_symbolic_name irqLine)
static inline void BSP_disable_main_irq_at_siu(
const rtems_irq_symbolic_name irqLine
)
{
uint8_t prio_index_offset;
uint32_t *reg;
@@ -346,25 +328,22 @@ static inline void BSP_disable_main_irq_at_siu(const rtems_irq_symbolic_name irq
/* disable (mask) main interrupt */
mpc5200.crit_pri_main_mask |= (0x80000000 >> SIU_MaskBit[irqLine]);
if((irqLine >= BSP_SIU_IRQ_IRQ1) && (irqLine <= BSP_SIU_IRQ_IRQ3))
{
if ((irqLine >= BSP_SIU_IRQ_IRQ1) && (irqLine <= BSP_SIU_IRQ_IRQ3)) {
/* disable external irq-pin */
mpc5200.ext_en_type &= ~(0x80000000 >> (20 + prio_index_offset));
}
/* reset priority to lowest level (reset value) */
reg = (uint32_t *)(&(mpc5200.main_pri_1));
reg += (irqLine >> 3);
*reg &= ~(15 << (28 - (prio_index_offset << 2)));
}
static inline void BSP_disable_crit_irq_at_siu(const rtems_irq_symbolic_name irqLine)
static inline void BSP_disable_crit_irq_at_siu(
const rtems_irq_symbolic_name irqLine
)
{
uint8_t prio_index_offset;
uint32_t *reg;
@@ -374,14 +353,10 @@ static inline void BSP_disable_crit_irq_at_siu(const rtems_irq_symbolic_name irq
reg = (uint32_t *)(&(mpc5200.crit_pri_main_mask));
*reg &= ~(3 << (30 - (prio_index_offset << 1)));
if(irqLine == BSP_SIU_IRQ_IRQ1)
{
if (irqLine == BSP_SIU_IRQ_IRQ1) {
/* disable external irq0-pin */
mpc5200.ext_en_type &= ~(0x80000000 >> (20 + prio_index_offset));
}
}
@@ -409,40 +384,26 @@ int BSP_irq_enable_at_siu(const rtems_irq_symbolic_name irqLine)
{
int base_index;
if(is_siu_irq(irqLine))
{
if((base_index = get_siu_irq_base_index(irqLine)) != -1)
{
switch(base_index)
{
if (is_siu_irq(irqLine)) {
if ((base_index = get_siu_irq_base_index(irqLine)) != -1) {
switch(base_index) {
case BSP_PER_IRQ_LOWEST_OFFSET:
BSP_enable_per_irq_at_siu(irqLine);
break;
case BSP_MAIN_IRQ_LOWEST_OFFSET:
BSP_enable_main_irq_at_siu(irqLine);
break;
case BSP_CRIT_IRQ_LOWEST_OFFSET:
BSP_enable_crit_irq_at_siu(irqLine);
break;
default:
printk("No valid base index\n");
break;
}
}
}
return 0;
}
/*
@@ -455,49 +416,39 @@ int BSP_irq_disable_at_siu(const rtems_irq_symbolic_name irqLine)
if ( (base_index = get_siu_irq_base_index(irqLine)) == -1)
return 1;
switch(base_index)
{
switch(base_index) {
case BSP_PER_IRQ_LOWEST_OFFSET:
BSP_disable_per_irq_at_siu(irqLine);
break;
case BSP_MAIN_IRQ_LOWEST_OFFSET:
BSP_disable_main_irq_at_siu(irqLine);
break;
case BSP_CRIT_IRQ_LOWEST_OFFSET:
BSP_disable_crit_irq_at_siu(irqLine);
break;
default:
printk("No valid base index\n");
break;
}
return 0;
}
/*
* ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
* --------------------- RTEMS Single Irq Handler Mngt Routines -------------
*/
/*
* This function removes the default entry and installs a device interrupt handler
* This function removes the default entry and installs a device
* interrupt handler
*/
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
if(!isValidInterrupt(irq->name))
{
if (!isValidInterrupt(irq->name)) {
printk("not a valid interrupt\n");
return 0;
}
/*
@@ -505,12 +456,9 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
* RATIONALE : to always have the same transition by forcing the user
* to get the previous handler before accepting to disconnect.
*/
if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl)
{
if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
printk( "Default handler not there\n" );
return 0;
}
rtems_interrupt_disable(level);
@@ -520,39 +468,23 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
*/
rtems_hdl_tbl[irq->name] = *irq;
if(is_siu_irq(irq->name))
{
if (is_siu_irq(irq->name)) {
/*
* Enable interrupt at siu level
*/
BSP_irq_enable_at_siu(irq->name);
}
else
{
if(is_processor_irq(irq->name))
{
} else {
if (is_processor_irq(irq->name)) {
/*
* Should Enable exception at processor level but not needed. Will restore
* EE flags at the end of the routine anyway.
* Should Enable exception at processor level but not needed.
* Will restore EE flags at the end of the routine anyway.
*/
}
else
{
} else {
printk("not a valid interrupt\n");
return 0;
}
}
/*
* Enable interrupt on device
*/
@@ -560,9 +492,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
irq->on(irq);
rtems_interrupt_enable(level);
return 1;
}
@@ -571,32 +501,24 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
*/
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq)
{
if(!isValidInterrupt(irq->name))
{
if (!isValidInterrupt(irq->name)) {
return 0;
}
*irq = rtems_hdl_tbl[irq->name];
return 1;
}
/*
* This function removes a device interrupt handler and restores the default entry
* This function removes a device interrupt handler and restores
* the default entry
*/
int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
if(!isValidInterrupt(irq->name))
{
if (!isValidInterrupt(irq->name)) {
return 0;
}
/*
@@ -604,27 +526,20 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* RATIONALE : to always have the same transition by forcing the user
* to get the previous handler before accepting to disconnect.
*/
if(rtems_hdl_tbl[irq->name].hdl != irq->hdl)
{
if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
return 0;
}
rtems_interrupt_disable(level);
if(is_siu_irq(irq->name))
{
if (is_siu_irq(irq->name)) {
/*
* disable interrupt at PIC level
*/
BSP_irq_disable_at_siu(irq->name);
}
if(is_processor_irq(irq->name))
{
if (is_processor_irq(irq->name)) {
/*
* disable exception at processor level
*/
@@ -644,16 +559,16 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
rtems_interrupt_enable(level);
return 1;
}
/*
* ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
* --------------------- RTEMS Global Irq Handler Mngt Routines -------------
*/
/*
* This function set up interrupt management dependent on the given configuration
* This function set up interrupt management dependent on the
* given configuration
*/
int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
{
@@ -672,63 +587,48 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
/*
* start with SIU IRQs
*/
for (i=BSP_SIU_IRQ_LOWEST_OFFSET; i < BSP_SIU_IRQ_LOWEST_OFFSET + BSP_SIU_IRQ_NUMBER ; i++)
{
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl)
{
for (i=BSP_SIU_IRQ_LOWEST_OFFSET;
i < BSP_SIU_IRQ_LOWEST_OFFSET + BSP_SIU_IRQ_NUMBER ;
i++) {
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
BSP_irq_enable_at_siu(i);
if (rtems_hdl_tbl[i].on)
rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
}
else
{
} else {
if (rtems_hdl_tbl[i].off)
rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
BSP_irq_disable_at_siu(i);
}
}
/*
* finish with Processor exceptions handled like IRQs
*/
for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++)
{
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl)
{
for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET;
i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER;
i++) {
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
if (rtems_hdl_tbl[i].on)
rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
}
else
{
} else {
if (rtems_hdl_tbl[i].off)
rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
}
}
rtems_interrupt_enable(level);
return 1;
}
int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
{
*config = internal_config;
return 0;
}
@@ -743,10 +643,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
register unsigned int pmce;
register unsigned int crit_pri_main_mask, per_mask;
switch(excNum)
{
switch (excNum) {
/*
* Handle decrementer interrupt
*/
@@ -762,21 +659,22 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
/* get the content of main interrupt status register */
pmce = mpc5200.pmce;
/* main interrupts may be routed to SMI, see bit SMI/INT select bit in main int. priorities */
while(CHK_MSE_STICKY(pmce))
{
/* check for main interrupt sources (hirarchical order) -> LO_int indicates peripheral sources */
if(CHK_MSE_STICKY(pmce))
{
/* main interrupts may be routed to SMI, see bit SMI/INT select
* bit in main int. priorities
*/
while (CHK_MSE_STICKY(pmce)) {
/* check for main interrupt sources (hirarchical order)
* -> LO_int indicates peripheral sources
*/
if (CHK_MSE_STICKY(pmce)) {
/* get source of main interrupt */
irq = MSE_SOURCE(pmce);
switch(irq) {
switch(irq)
{
/* irq1-3, RTC, GPIO, TMR0-7 detected (attention: slice timer 2 is always routed to SMI) */
/* irq1-3, RTC, GPIO, TMR0-7 detected (attention:
* slice timer 2 is always routed to SMI)
*/
case 0: /* slice timer 2 */
case 1:
case 2:
@@ -794,10 +692,14 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
case 15:
case 16:
/* add proper offset for main interrupts in the siu handler array */
/* add proper offset for main interrupts in
* the siu handler array
*/
irq += BSP_MAIN_IRQ_LOWEST_OFFSET;
/* save original mask and disable all lower priorized main interrupts*/
/* save original mask and disable all lower
* priorized main interrupts
*/
crit_pri_main_mask = mpc5200.crit_pri_main_mask;
mpc5200.crit_pri_main_mask |= irqMaskTable[irq];
@@ -806,7 +708,9 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
/* call the module specific handler and pass the specific handler */
/* call the module specific handler and pass the
* specific handler
*/
rtems_hdl_tbl[irq].hdl(0);
/* disable interrupt nesting */
@@ -821,16 +725,18 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
case 4:
/* check for valid peripheral interrupt source */
if(CHK_PSE_STICKY(pmce))
{
if (CHK_PSE_STICKY(pmce)) {
/* get source of peripheral interrupt */
irq = PSE_SOURCE(pmce);
/* add proper offset for peripheral interrupts in the siu handler array */
/* add proper offset for peripheral interrupts
* in the siu handler array
*/
irq += BSP_PER_IRQ_LOWEST_OFFSET;
/* save original mask and disable all lower priorized main interrupts */
/* save original mask and disable all lower
* priorized main interrupts
*/
per_mask = mpc5200.per_mask;
mpc5200.per_mask |= irqMaskTable[irq];
@@ -839,10 +745,11 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
/* call the module specific handler and pass the specific handler */
/* call the module specific handler and pass
* the specific handler
*/
rtems_hdl_tbl[irq].hdl(0);
/* disable interrupt nesting */
_CPU_MSR_SET(msr);
@@ -851,82 +758,72 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
/* force re-evaluation of peripheral interrupts */
CLR_PSE_STICKY(mpc5200.pmce);
}
/* this case may not occur: no valid peripheral interrupt source */
else
{
} else {
/* this case may not occur: no valid peripheral
* interrupt source
*/
printk("No valid peripheral LO_int interrupt source\n");
}
break;
/* error: unknown interrupt source */
default:
printk("Unknown peripheral LO_int interrupt source\n");
break;
}
/* force re-evaluation of main interrupts */
CLR_MSE_STICKY(mpc5200.pmce);
}
/* get the content of main interrupt status register */
pmce = mpc5200.pmce;
}
break;
case ASM_EXT_VECTOR:
/* get the content of main interrupt status register */
pmce = mpc5200.pmce;
/* critical interrupts may be routed to the core_int dependent on premature initialization, see bit 31 (CEbsH) */
while((CHK_CE_SHADOW(pmce) && CHK_CSE_STICKY(pmce)) || CHK_MSE_STICKY(pmce) || CHK_PSE_STICKY(pmce) )
{
/* first: check for critical interrupt sources (hirarchical order) -> HI_int indicates peripheral sources */
if(CHK_CE_SHADOW(pmce) && CHK_CSE_STICKY(pmce))
{
/* critical interrupts may be routed to the core_int
* dependent on premature initialization, see bit 31 (CEbsH)
*/
while((CHK_CE_SHADOW(pmce) && CHK_CSE_STICKY(pmce)) ||
CHK_MSE_STICKY(pmce) || CHK_PSE_STICKY(pmce) ) {
/* first: check for critical interrupt sources (hierarchical order)
* -> HI_int indicates peripheral sources
*/
if (CHK_CE_SHADOW(pmce) && CHK_CSE_STICKY(pmce)) {
/* get source of critical interrupt */
irq = CSE_SOURCE(pmce);
switch(irq)
{
switch(irq) {
/* irq0, slice timer 1 or ccs wakeup detected */
case 0:
case 1:
case 3:
/* add proper offset for critical interrupts in the siu handler array */
/* add proper offset for critical interrupts in the siu
* handler array */
irq += BSP_CRIT_IRQ_LOWEST_OFFSET;
/* call the module specific handler and pass the specific handler */
/* call the module specific handler and pass the
* specific handler */
rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
break;
/* peripheral HI_int interrupt source detected */
case 2:
/* check for valid peripheral interrupt source */
if(CHK_PSE_STICKY(pmce))
{
if (CHK_PSE_STICKY(pmce)) {
/* get source of peripheral interrupt */
irq = PSE_SOURCE(pmce);
/* add proper offset for peripheral interrupts in the siu handler array */
/* add proper offset for peripheral interrupts in the
* siu handler array */
irq += BSP_PER_IRQ_LOWEST_OFFSET;
/* save original mask and disable all lower priorized main interrupts */
/* save original mask and disable all lower
* priorized main interrupts */
per_mask = mpc5200.per_mask;
mpc5200.per_mask |= irqMaskTable[irq];
@@ -935,11 +832,10 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
/* call the module specific handler and pass the specific handler */
/* call the module specific handler and pass the
* specific handler */
rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
/* disable interrupt nesting */
_CPU_MSR_SET(msr);
/* restore original interrupt mask */
@@ -947,41 +843,31 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
/* force re-evaluation of peripheral interrupts */
CLR_PSE_STICKY(mpc5200.pmce);
}
/* this case may not occur: no valid peripheral interrupt source */
else
{
} else {
/* this case may not occur: no valid peripheral
* interrupt source */
printk("No valid peripheral HI_int interrupt source\n");
}
break;
/* error: unknown interrupt source */
default:
/* error: unknown interrupt source */
printk("Unknown HI_int interrupt source\n");
break;
}
/* force re-evaluation of critical interrupts */
CLR_CSE_STICKY(mpc5200.pmce);
}
/* second: check for main interrupt sources (hirarchical order) -> LO_int indicates peripheral sources */
if(CHK_MSE_STICKY(pmce))
{
/* second: check for main interrupt sources (hierarchical order)
* -> LO_int indicates peripheral sources */
if (CHK_MSE_STICKY(pmce)) {
/* get source of main interrupt */
irq = MSE_SOURCE(pmce);
switch(irq)
{
switch (irq) {
/* irq1-3, RTC, GPIO, TMR0-7 detected (attention: slice timer 2 is always routed to SMI) */
/* irq1-3, RTC, GPIO, TMR0-7 detected (attention: slice timer
* 2 is always routed to SMI) */
case 1:
case 2:
case 3:
@@ -997,11 +883,12 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
case 14:
case 15:
case 16:
/* add proper offset for main interrupts in the siu handler array */
/* add proper offset for main interrupts in the siu
* handler array */
irq += BSP_MAIN_IRQ_LOWEST_OFFSET;
/* save original mask and disable all lower priorized main interrupts*/
/* save original mask and disable all lower priorized
* main interrupts*/
crit_pri_main_mask = mpc5200.crit_pri_main_mask;
mpc5200.crit_pri_main_mask |= irqMaskTable[irq];
@@ -1010,7 +897,8 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
/* call the module specific handler and pass the specific handler */
/* call the module specific handler and pass the specific
* handler */
rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
/* disable interrupt nesting */
@@ -1018,23 +906,21 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
/* restore original interrupt mask */
mpc5200.crit_pri_main_mask = crit_pri_main_mask;
break;
/* peripheral LO_int interrupt source detected */
case 4:
/* check for valid peripheral interrupt source */
if(CHK_PSE_STICKY(pmce))
{
if (CHK_PSE_STICKY(pmce)) {
/* get source of peripheral interrupt */
irq = PSE_SOURCE(pmce);
/* add proper offset for peripheral interrupts in the siu handler array */
/* add proper offset for peripheral interrupts in the siu
* handler array */
irq += BSP_PER_IRQ_LOWEST_OFFSET;
/* save original mask and disable all lower priorized main interrupts */
/* save original mask and disable all lower priorized main
* interrupts */
per_mask = mpc5200.per_mask;
mpc5200.per_mask |= irqMaskTable[irq];
@@ -1043,10 +929,10 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
/* call the module specific handler and pass the specific handler */
/* call the module specific handler and pass the
* specific handler */
rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
/* disable interrupt nesting */
_CPU_MSR_SET(msr);
@@ -1055,36 +941,24 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
/* force re-evaluation of peripheral interrupts */
CLR_PSE_STICKY(mpc5200.pmce);
}
/* this case may not occur: no valid peripheral interrupt source */
else
{
} else {
/* this case may not occur: no valid peripheral
* interrupt source */
printk("No valid peripheral LO_int interrupt source\n");
}
break;
/* error: unknown interrupt source */
default:
printk("Unknown peripheral LO_int interrupt source\n");
break;
}
/* force re-evaluation of main interrupts */
CLR_MSE_STICKY(mpc5200.pmce);
}
/* get the content of main interrupt status register */
pmce = mpc5200.pmce;
}
break;
default:
@@ -1092,9 +966,6 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
break;
} /* end of switch(excNum) */
return;
}