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2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>

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PR 1573/cpukit
	* arm_exc_interrupt.S: Add a per cpu data structure which contains the
	information required by RTEMS for each CPU core. This encapsulates
	information such as thread executing, heir, idle and dispatch needed.
This commit is contained in:
Joel Sherrill
2010-06-29 00:31:02 +00:00
parent 46cce26f70
commit b616350ec9
2 changed files with 11 additions and 15 deletions
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7
cpukit/score/cpu/arm/ChangeLog
View File

@@ -1,3 +1,10 @@
2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>
PR 1573/cpukit
* arm_exc_interrupt.S: Add a per cpu data structure which contains the
information required by RTEMS for each CPU core. This encapsulates
information such as thread executing, heir, idle and dispatch needed.
2010-05-10 Joel Sherrill <joel.sherrilL@OARcorp.com> 2010-05-10 Joel Sherrill <joel.sherrilL@OARcorp.com>
* rtems/score/arm.h: Make it a warning not error that the FPU multilib * rtems/score/arm.h: Make it a warning not error that the FPU multilib

19
cpukit/score/cpu/arm/arm_exc_interrupt.S
View File

@@ -30,6 +30,7 @@
#endif #endif
#include <rtems/asm.h> #include <rtems/asm.h>
#include <rtems/score/percpu.h>
#define EXCHANGE_LR r4 #define EXCHANGE_LR r4
#define EXCHANGE_SPSR r5 #define EXCHANGE_SPSR r5
@@ -42,9 +43,6 @@
#define CONTEXT_LIST {r0, r1, r2, r3, EXCHANGE_LR, EXCHANGE_SPSR, r12} #define CONTEXT_LIST {r0, r1, r2, r3, EXCHANGE_LR, EXCHANGE_SPSR, r12}
#define CONTEXT_SIZE 28 #define CONTEXT_SIZE 28
.extern _ISR_Nest_level
.extern _ISR_Signals_to_thread_executing
.extern _ISR_Thread_dispatch
.extern _Thread_Dispatch_disable_level .extern _Thread_Dispatch_disable_level
.extern bsp_interrupt_dispatch .extern bsp_interrupt_dispatch
@@ -81,7 +79,7 @@ arm_exc_interrupt:
ldmia r1, EXCHANGE_LIST ldmia r1, EXCHANGE_LIST
/* Get interrupt nest level */ /* Get interrupt nest level */
ldr r0, =_ISR_Nest_level ldr r0, =ISR_NEST_LEVEL
ldr r2, [r0] ldr r2, [r0]
/* Switch stack if necessary and save original stack pointer */ /* Switch stack if necessary and save original stack pointer */
@@ -105,7 +103,7 @@ arm_exc_interrupt:
bl bsp_interrupt_dispatch bl bsp_interrupt_dispatch
/* Decrement interrupt nest and thread dispatch disable level */ /* Decrement interrupt nest and thread dispatch disable level */
ldr r0, =_ISR_Nest_level ldr r0, =ISR_NEST_LEVEL
ldr r1, =_Thread_Dispatch_disable_level ldr r1, =_Thread_Dispatch_disable_level
ldr r2, [r0] ldr r2, [r0]
ldr r3, [r1] ldr r3, [r1]
@@ -124,13 +122,7 @@ arm_exc_interrupt:
bne thread_dispatch_done bne thread_dispatch_done
/* Check context switch necessary */ /* Check context switch necessary */
ldr r0, =_Context_Switch_necessary ldr r0, =DISPATCH_NEEDED
ldrb r1, [r0]
ldr r0, =_ISR_Signals_to_thread_executing
cmp r1, #0
bne do_thread_dispatch
/* Check ISR signals to thread executing */
ldrb r1, [r0] ldrb r1, [r0]
cmp r1, #0 cmp r1, #0
beq thread_dispatch_done beq thread_dispatch_done
@@ -142,9 +134,6 @@ arm_exc_interrupt:
do_thread_dispatch: do_thread_dispatch:
/* Clear ISR signals to thread executing */
strb r3, [r0]
/* Thread dispatch */ /* Thread dispatch */
bl _Thread_Dispatch bl _Thread_Dispatch