RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

2010-11-16 Gedare Bloom <giddyup44@yahoo.com>

Browse Source 
PR 1691/bsps
	* shared/clock/ckinit.c: The sparc64/shared/clock driver has
	a bug that causes nested timer interrupts to not be serviced,
	which leads to non-preemptive behavior especially when dispatching
	work from the timer ISR.
This commit is contained in:
Joel Sherrill
2010-11-16 23:22:13 +00:00
parent 722c0fdfdf
commit b5df1f9a7d
2 changed files with 14 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
c/src/lib/libbsp/sparc64/ChangeLog
View File

@@ -1,3 +1,11 @@
2010-11-16 Gedare Bloom <giddyup44@yahoo.com>
PR 1691/bsps
* shared/clock/ckinit.c: The sparc64/shared/clock driver has
a bug that causes nested timer interrupts to not be serviced,
which leads to non-preemptive behavior especially when dispatching
work from the timer ISR.
2010-11-15 Gedare Bloom <giddyup44@yahoo.com>
PR 1691/bsps

8
c/src/lib/libbsp/sparc64/shared/clock/ckinit.c
View File

@@ -50,11 +50,16 @@ void Clock_driver_support_at_tick(void)
{
uint64_t tick_reg;
int bit_mask;
uint64_t pil_reg;
bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14);
sparc64_clear_interrupt_bits(bit_mask);
sparc64_get_pil(pil_reg);
if(pil_reg == 0xe) { /* 0xe is the tick compare interrupt (softint(14)) */
pil_reg--;
sparc64_set_pil(pil_reg); /* enable the next timer interrupt */
}
/* Note: sun4v uses stick_cmpr for clock driver for M5 simulator, which
* does not currently have tick_cmpr implemented */
/* TODO: this could be more efficiently implemented as a single assembly
@@ -85,7 +90,6 @@ void Clock_driver_support_initialize_hardware(void)
uint64_t tick_reg;
int bit_mask;
bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14);
sparc64_clear_interrupt_bits(bit_mask);