forked from Imagelibrary/rtems
2011-27-28 Till Straumann <strauman@slac.stanford.edu>
* start/start.S: fixed indentation. Tag TOS with a NULL pointer (help terminate when walking the stack).
This commit is contained in:
Till Straumann
@@ -1,3 +1,8 @@
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2011-27-28 Till Straumann <strauman@slac.stanford.edu>
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* start/start.S: fixed indentation. Tag TOS with a NULL
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pointer (help terminate when walking the stack).
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2011-06-17 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* Makefile.am: Added custom memcpy(). Update for network sources.
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@@ -222,7 +222,7 @@ __vecf: b __vecf
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PUBLIC_VAR (start)
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start:
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/* 1st: initialization work (common for RAM/ROM startup) */
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mfmsr r30
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mfmsr r30
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SETBITS r30, r29, MSR_ME|MSR_RI
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CLRBITS r30, r29, MSR_EE
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mtmsr r30 /* Set RI/ME, Clr EE in MSR */
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@@ -442,19 +442,19 @@ skip_ROM_start:
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/* clear entire on chip SRAM (unique for ROM startup) */
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lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */
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ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
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LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
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LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
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bl clr_mem /* Clear onchip SRAM */
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bl clr_mem /* Clear onchip SRAM */
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#else /* defined(NEED_LOW_LEVEL_INIT) */
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bl XLB_init
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#endif /* defined(NEED_LOW_LEVEL_INIT) */
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/* clear .bss section (unique for ROM startup) */
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LWI r30, bsp_section_bss_start /* get start address of bss section */
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LWI r29, bsp_section_bss_size /* get size of bss section */
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LWI r29, bsp_section_bss_size /* get size of bss section */
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bl clr_mem /* Clear the bss section */
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bl clr_mem /* Clear the bss section */
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#ifdef HAS_UBOOT
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mr r3, r14
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@@ -463,7 +463,10 @@ skip_ROM_start:
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/* set stack pointer (common for RAM/ROM startup) */
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LA r1, bsp_section_text_start
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addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
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addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
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/* tag TOS with a NULL pointer (termination mark for stack dump) */
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li r0, 0
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stw r0, 0(r1)
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bl __eabi /* Set up EABI and SYSV environment */
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@@ -475,10 +478,10 @@ skip_ROM_start:
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/* clear arguments and do further init. in C (common for RAM/ROM startup) */
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/* Clear cmdline */
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xor r3, r3, r3
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/* Clear cmdline */
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xor r3, r3, r3
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bl SYM (boot_card) /* Call the first C routine */
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bl SYM (boot_card) /* Call the first C routine */
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twiddle:
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b twiddle /* We don't expect to return from boot_card but if we do */
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@@ -507,7 +510,7 @@ SDRAM_init:
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or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */
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stw r29,GPIOWDD(r31)
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/* activate MEM_CS1 output */
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/* activate MEM_CS1 output */
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lwz r29, GPIOPCR(r31)
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or r29,r29,r30 /* set bit 0 in r29/GPIOPCR */
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stw r29,GPIOPCR(r31)
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@@ -625,20 +628,20 @@ copy_image_end:
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FID_DCache:
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mflr r26
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bl PPC_HID0_rd
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TSTBITS r30, r29, HID0_DCE
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bne FID_DCache_exit /* If data cache is switched of, skip further actions */
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bl PPC_HID0_rd
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TSTBITS r30, r29, HID0_DCE
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bne FID_DCache_exit /* If data cache is switched of, skip further actions */
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li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
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LWI r28, bsp_section_text_start /* Load base address (begin of RAM) */
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FID_DCache_loop_1:
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lwz r27, 0(r28) /* Load data at address */
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lwz r27, 0(r28) /* Load data at address */
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addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
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subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
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cmpwi r29, 0x0
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bne FID_DCache_loop_1 /* Loop until cache size is reached */
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addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
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subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
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cmpwi r29, 0x0
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bne FID_DCache_loop_1 /* Loop until cache size is reached */
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li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
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LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */
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@@ -647,14 +650,14 @@ FID_DCache_loop_2:
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dcbf r27, r28 /* Flush and invalidate cache */
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addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
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addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
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subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
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cmpwi r29, 0x0
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bne FID_DCache_loop_2 /* Loop around until cache size is reached */
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bne FID_DCache_loop_2 /* Loop around until cache size is reached */
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bl PPC_HID0_rd /* Read HID0 */
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CLRBITS r30, r29, HID0_DCE
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bl PPC_HID0_wr /* Clear DCE */
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bl PPC_HID0_rd /* Read HID0 */
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CLRBITS r30, r29, HID0_DCE
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bl PPC_HID0_wr /* Clear DCE */
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FID_DCache_exit:
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mtlr r26
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@@ -663,21 +666,21 @@ FID_DCache_exit:
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IDUL_ICache:
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mflr r26
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bl PPC_HID0_rd
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TSTBITS r30, r29, HID0_ICE
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bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */
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bl PPC_HID0_rd
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TSTBITS r30, r29, HID0_ICE
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bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */
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CLRBITS r30, r29, HID0_ICE
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bl PPC_HID0_wr /* Disable ICE bit */
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bl PPC_HID0_wr /* Disable ICE bit */
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SETBITS r30, r29, HID0_ICFI
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bl PPC_HID0_wr /* Invalidate instruction cache */
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bl PPC_HID0_wr /* Invalidate instruction cache */
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CLRBITS r30, r29, HID0_ICFI
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bl PPC_HID0_wr /* Disable cache invalidate */
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CLRBITS r30, r29, HID0_ICFI
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bl PPC_HID0_wr /* Disable cache invalidate */
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CLRBITS r30, r29, HID0_ILOCK
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bl PPC_HID0_wr /* Disable instruction cache lock */
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CLRBITS r30, r29, HID0_ILOCK
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bl PPC_HID0_wr /* Disable instruction cache lock */
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IDUL_ICache_exit:
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mtlr r26
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@@ -854,47 +857,47 @@ SPRG_brk_init:
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PPC_HID0_rd: /* get HID0 content to r30 */
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mfspr r30, HID0
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mfspr r30, HID0
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blr
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blr
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PPC_HID0_wr: /* put r30 content to HID0 */
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mtspr HID0, r30
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mtspr HID0, r30
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blr
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blr
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clr_mem:
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mr r28, r29
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srwi r29, r29, 2
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mtctr r29 /* set ctr reg */
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mtctr r29 /* set ctr reg */
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slwi r29, r29, 2
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sub r28, r28, r29 /* maybe some residual bytes */
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xor r29, r29, r29
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slwi r29, r29, 2
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sub r28, r28, r29 /* maybe some residual bytes */
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xor r29, r29, r29
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clr_mem_word:
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stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
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addi r30, r30, 0x04 /* increment r30 */
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stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
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addi r30, r30, 0x04 /* increment r30 */
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bdnz clr_mem_word /* dec counter and loop */
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bdnz clr_mem_word /* dec counter and loop */
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cmpwi r28, 0x00 /* clear mem. finished ? */
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beq clr_mem_end;
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mtctr r28 /* reload counter for residual bytes */
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mtctr r28 /* reload counter for residual bytes */
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clr_mem_byte:
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stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */
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addi r30, r30, 0x01 /* update r30 */
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bdnz clr_mem_byte /* dec counter and loop */
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bdnz clr_mem_byte /* dec counter and loop */
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clr_mem_end:
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blr /* return */
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blr /* return */
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XLB_init:
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/* init arbiter and stuff... */
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