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2000-12-13 Joel Sherrill <joel@OARcorp.com>

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* shared/.cvsignore, shared/Makefile.am,
	shared/cache/.cvsignore, shared/cache/Makefile.am,
	shared/cache/cache.c, shared/cache/cache_.h,
	shared/interrupts/.cvsignore, shared/interrupts/Makefile.am,
	shared/interrupts/installisrentries.c,
	shared/interrupts/isr_entries.S,
	shared/interrupts/maxvectors.c, tx39/.cvsignore,
	tx39/Makefile.am, tx39/include/.cvsignore,
	tx39/include/Makefile.am, tx39/include/tx3904.h: New file.
	Moved some pieces of interrupt processing from score/cpu to
	libcpu/mips since many interrupt servicing characteristics are
	CPU model dependent.  This patch addresses the number of interrupt
	sources and where the ISR prologues are located.  The only way to
	currently install the ISR prologues requires that the prologues
	be installed into RAM.
This commit is contained in:
Joel Sherrill
2000-12-13 17:52:53 +00:00
parent 2a350da55b
commit b4d0d18eed
20 changed files with 396 additions and 3 deletions
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74
c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S Normal file
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/*
* This file contains the raw entry points for the exceptions.
*
* COPYRIGHT (c) 1989-2000.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
/* @(#)cpu_asm.S 08/20/96 1.15 */
#include <asm.h>
#include "iregdef.h"
#include "idtcpu.h"
/*
* MIPS ISA Level 1 entries
*/
#if __mips == 1
FRAME(exc_norm_code,sp,0,ra)
la k0, _ISR_Handler /* generic external int hndlr */
j k0
nop
ENDFRAME(exc_norm_code)
/* XXX this is dependent on IDT/SIM and needs to be addressed */
FRAME(exc_utlb_code,sp,0,ra)
la k0, (R_VEC+((48)*8))
j k0
nop
ENDFRAME(exc_tlb_code)
/*
* MIPS ISA Level 3
* XXX Again, reliance on SIM. Not good.
*/
#elif __mips == 3
FRAME(exc_tlb_code,sp,0,ra)
la k0, (R_VEC+((112)*8)) /* R4000 Sim location */
j k0
nop
ENDFRAME(exc_tlb_code)
FRAME(exc_xtlb_code,sp,0,ra)
la k0, (R_VEC+((112)*8)) /* R4000 Sim location */
j k0
nop
ENDFRAME(exc_xtlb_code)
FRAME(exc_cache_code,sp,0,ra)
la k0, (R_VEC+((112)*8)) /* R4000 Sim location */
j k0
nop
ENDFRAME(exc_cache_code)
FRAME(exc_norm_code,sp,0,ra)
la k0, _ISR_Handler /* generic external int hndlr */
j k0
nop
ENDFRAME(exc_norm_code)
#else
#error "isr_entries.S: ISA support problem"
#endif