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2000-12-13 Joel Sherrill <joel@OARcorp.com>

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* shared/.cvsignore, shared/Makefile.am,
	shared/cache/.cvsignore, shared/cache/Makefile.am,
	shared/cache/cache.c, shared/cache/cache_.h,
	shared/interrupts/.cvsignore, shared/interrupts/Makefile.am,
	shared/interrupts/installisrentries.c,
	shared/interrupts/isr_entries.S,
	shared/interrupts/maxvectors.c, tx39/.cvsignore,
	tx39/Makefile.am, tx39/include/.cvsignore,
	tx39/include/Makefile.am, tx39/include/tx3904.h: New file.
	Moved some pieces of interrupt processing from score/cpu to
	libcpu/mips since many interrupt servicing characteristics are
	CPU model dependent.  This patch addresses the number of interrupt
	sources and where the ISR prologues are located.  The only way to
	currently install the ISR prologues requires that the prologues
	be installed into RAM.
This commit is contained in:
Joel Sherrill
2000-12-13 17:52:53 +00:00
parent 2a350da55b
commit b4d0d18eed
20 changed files with 396 additions and 3 deletions
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29
c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c Normal file
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@@ -0,0 +1,29 @@
/*
* $Id$
*/
#include <rtems.h>
#include <idtcpu.h>
#include <stdlib.h>
void mips_install_isr_entries( void )
{
#if __mips == 1
void exc_utlb_code(void);
void exc_norm_code(void);
memcpy( (void *)UT_VEC, exc_utlb_code, 40 ); /* utlbmiss vector */
memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vevtor */
#elif __mips == 3
void exc_tlb_code(void);
void exc_utlb_code(void);
void exc_cache_code(void);
void exc_norm_code(void);
memcpy( (void *)T_VEC, exc_tlb_code, 40 ); /* tlbmiss vector */
memcpy( (void *)X_VEC, exc_xtlb_code, 40 ); /* xtlbmiss vector */
memcpy( (void *)C_VEC, exc_cache_code, 40 ); /* cache error vector */
memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vector */
#endif
rtems_cache_flush_entire_data();
}