2000-12-13 Joel Sherrill <joel@OARcorp.com>

* shared/.cvsignore, shared/Makefile.am,
	shared/cache/.cvsignore, shared/cache/Makefile.am,
	shared/cache/cache.c, shared/cache/cache_.h,
	shared/interrupts/.cvsignore, shared/interrupts/Makefile.am,
	shared/interrupts/installisrentries.c,
	shared/interrupts/isr_entries.S,
	shared/interrupts/maxvectors.c, tx39/.cvsignore,
	tx39/Makefile.am, tx39/include/.cvsignore,
	tx39/include/Makefile.am, tx39/include/tx3904.h: New file.
	Moved some pieces of interrupt processing from score/cpu to
	libcpu/mips since many interrupt servicing characteristics are
	CPU model dependent.  This patch addresses the number of interrupt
	sources and where the ISR prologues are located.  The only way to
	currently install the ISR prologues requires that the prologues
	be installed into RAM.

c/src/lib/libcpu/mips/shared/interrupts/.cvsignore

@@ -0,0 +1,2 @@
+Makefile
+Makefile.in

c/src/lib/libcpu/mips/shared/interrupts/Makefile.am

@@ -0,0 +1,32 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = $(ARCH)/interrupts.rel
+
+C_FILES = installisrentries.c maxvectors.c
+
+S_FILES = isr_entries.S
+
+interrupts_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../automake/compile.am
+include $(top_srcdir)/../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+$(PGM): $(interrupts_rel_OBJECTS)
+	$(make-rel)
+
+all-local: $(ARCH) $(interrupts_rel_OBJECTS) $(PGM)
+
+.PRECIOUS: $(PGM)
+
+EXTRA_DIST = maxvectors.c
+
+include $(top_srcdir)/../../../../../automake/local.am

c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c

@@ -0,0 +1,29 @@
+/*
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <idtcpu.h>
+#include <stdlib.h>
+
+void mips_install_isr_entries( void )
+{
+#if __mips == 1
+  void exc_utlb_code(void);
+  void exc_norm_code(void);
+
+  memcpy( (void *)UT_VEC, exc_utlb_code, 40 );  /* utlbmiss vector */
+  memcpy( (void *)E_VEC, exc_norm_code, 40 );   /* exception vevtor */
+#elif __mips == 3
+  void exc_tlb_code(void);
+  void exc_utlb_code(void);
+  void exc_cache_code(void);
+  void exc_norm_code(void);
+
+  memcpy( (void *)T_VEC, exc_tlb_code, 40 );    /* tlbmiss vector */
+  memcpy( (void *)X_VEC, exc_xtlb_code, 40 );   /* xtlbmiss vector */
+  memcpy( (void *)C_VEC, exc_cache_code, 40 );  /* cache error vector */
+  memcpy( (void *)E_VEC, exc_norm_code, 40 );   /* exception vector */
+#endif
+  rtems_cache_flush_entire_data();
+}

c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S

@@ -0,0 +1,74 @@
+/*
+ *  This file contains the raw entry points for the exceptions.
+ *
+ *  COPYRIGHT (c) 1989-2000.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+/* @(#)cpu_asm.S       08/20/96     1.15 */
+
+#include <asm.h>
+#include "iregdef.h"
+#include "idtcpu.h"
+
+/*
+ *  MIPS ISA Level 1 entries
+ */
+
+#if __mips == 1
+
+FRAME(exc_norm_code,sp,0,ra)
+	la	k0, _ISR_Handler /* generic external int hndlr */
+	j	k0
+	nop
+ENDFRAME(exc_norm_code)
+
+/* XXX this is dependent on IDT/SIM and needs to be addressed */
+FRAME(exc_utlb_code,sp,0,ra)
+        la      k0, (R_VEC+((48)*8))
+        j       k0
+	nop
+ENDFRAME(exc_tlb_code)
+
+/* 
+ * MIPS ISA Level 3
+ * XXX Again, reliance on SIM. Not good.
+ */
+#elif __mips == 3
+
+FRAME(exc_tlb_code,sp,0,ra)
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
+        j       k0
+	nop
+ENDFRAME(exc_tlb_code)
+
+FRAME(exc_xtlb_code,sp,0,ra)
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
+        j       k0
+	nop
+
+ENDFRAME(exc_xtlb_code)
+
+FRAME(exc_cache_code,sp,0,ra)
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
+        j       k0
+	nop
+ENDFRAME(exc_cache_code)
+
+FRAME(exc_norm_code,sp,0,ra)
+	la	k0, _ISR_Handler /* generic external int hndlr */
+	j	k0
+	nop
+ENDFRAME(exc_norm_code)
+
+#else
+
+#error "isr_entries.S: ISA support problem"
+
+#endif
+

c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c

@@ -0,0 +1,29 @@
+/* 
+ *  This file contains the maximum number of vectors.  This can not
+ *  be determined without knowing the RTEMS CPU model. 
+ *
+ *  COPYRIGHT (c) 1989-2000.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+
+/*
+ *  The tx3904 attaches 4 of the eight interrupt bits to an on-CPU interrupt
+ *  controller so that these four bits map to 16 unique interrupts.
+ *  So you have: 2 software interrupts, an NMI, and 16 others.
+ */
+#if defined(tx3904)
+#define MAX_VECTORS 19
+#endif
+
+#ifndef MAX
+#define MAX_VECTORS 8
+#endif
+
+unsigned int mips_interrupt_number_of_vectors = MAX_VECTORS;