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2005-03-04 Joel Sherrill <joel@OARcorp.com>

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* include/rtems/pci.h: Clean up and reformatting. Make PCI initialize
	function part of the unified PCI API.
This commit is contained in:
Joel Sherrill
2005-03-04 21:47:36 +00:00
parent f28dcc9183
commit b3f80031c7
2 changed files with 1106 additions and 1048 deletions
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5
cpukit/ChangeLog
View File

@@ -1,3 +1,8 @@
2005-03-04 Joel Sherrill <joel@OARcorp.com>
* include/rtems/pci.h: Clean up and reformatting. Make PCI initialize
function part of the unified PCI API.
2005-03-04 Ralf Corsepius <ralf.corsepius@rtems.org>
* configure.ac: Check for newlib with stdint.h/inttypes.h.

161
cpukit/include/rtems/pci.h
View File

@@ -24,42 +24,41 @@
*/
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_COMMAND_IO 0x0001 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x0002 /* Enable response in Memory space */
#define PCI_COMMAND_MASTER 0x0004 /* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x0008 /* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x0010 /* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE 0x0020 /* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x0040 /* Enable parity checking */
#define PCI_COMMAND_WAIT 0x0080 /* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x0100 /* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x0200 /* Enable back-to-back writes */
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features */
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define PCI_STATUS_66MHZ 0x0020 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x0040 /* Support User Definable Features */
#define PCI_STATUS_FAST_BACK 0x0080 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x0100 /* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK 0x0600 /* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x0000
#define PCI_STATUS_DEVSEL_MEDIUM 0x0200
#define PCI_STATUS_DEVSEL_SLOW 0x0400
#define PCI_STATUS_SIG_TARGET_ABORT 0x0800 /* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
revision */
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
#define PCI_REVISION_ID 0x08 /* Revision ID */
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
@@ -98,7 +97,7 @@
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
#define PCI_SUBSYSTEM_ID 0x2e
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS 0x30/* Bits 31..11 address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE 0x01
#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
@@ -119,7 +118,9 @@
#define PCI_IO_RANGE_TYPE_16 0x00
#define PCI_IO_RANGE_TYPE_32 0x01
#define PCI_IO_RANGE_MASK ~0x0f
#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
#define PCI_MEMORY_LIMIT 0x22
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
@@ -130,7 +131,7 @@
#define PCI_PREF_RANGE_TYPE_32 0x00
#define PCI_PREF_RANGE_TYPE_64 0x01
#define PCI_PREF_RANGE_MASK ~0x0f
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory */
#define PCI_PREF_LIMIT_UPPER32 0x2c
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16 0x32
@@ -144,7 +145,8 @@
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled */
/* on secondary interface */
/* Header type 2 (CardBus bridges) */
/* 0x14-0x15 reserved */
@@ -167,20 +169,28 @@
#define PCI_CB_IO_LIMIT_1_HI 0x3a
#define PCI_CB_IO_RANGE_MASK ~0x03
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL 0x3e
#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge */
/* control register */
#define PCI_CB_BRIDGE_CTL_SERR 0x02
#define PCI_CB_BRIDGE_CTL_ISA 0x04
#define PCI_CB_BRIDGE_CTL_VGA 0x08
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for */
/* 16-bit cards */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for */
/* both memory regions */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
#define PCI_CB_SUBSYSTEM_ID 0x42
#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
/* 16-bit PC Card legacy mode base address (ExCa) */
#define PCI_CB_LEGACY_MODE_BASE 0x44
/* 0x48-0x7f reserved */
/* Device classes and subclasses */
@@ -491,7 +501,6 @@
#define PCI_VENDOR_ID_OAK 0x104e
#define PCI_DEVICE_ID_OAK_OTI107 0x0107
/* Winbond have two vendor IDs! See 0x10ad as well */
#define PCI_VENDOR_ID_WINBOND2 0x1050
#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940
@@ -1058,7 +1067,6 @@
#define PCI_DEVICE_ID_ARK_STING 0xa091
#define PCI_DEVICE_ID_ARK_STINGARK 0xa099
#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1
/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded
@@ -1067,9 +1075,9 @@
* 7:3 = slot
* 2:0 = function
*/
#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
#define PCI_FUNC(devfn) ((devfn) & 0x07)
#define PCI_DEVFN(_slot,_func) ((((_slot) & 0x1f) << 3) | ((_func) & 0x07))
#define PCI_SLOT(_devfn) (((_devfn) >> 3) & 0x1f)
#define PCI_FUNC(_devfn) ((_devfn) & 0x07)
/*
* Error values that may be returned by the PCI bios.
@@ -1101,7 +1109,18 @@ typedef struct {
unsigned char, unsigned short);
int (*write_config_dword)(unsigned char, unsigned char, unsigned char,
unsigned char, unsigned int);
}pci_config_access_functions;
} pci_config_access_functions;
/* Error codes for pci_initialize */
#define PCIB_ERR_SUCCESS (0)
#define PCIB_ERR_UNINITIALIZED (-1) /* PCI BIOS is not initilized */
#define PCIB_ERR_NOTPRESENT (-2) /* PCI BIOS not present */
#define PCIB_ERR_NOFUNC (-3) /* Function not supported */
#define PCIB_ERR_BADVENDOR (-4) /* Bad Vendor ID */
#define PCIB_ERR_DEVNOTFOUND (-5) /* Device not found */
#define PCIB_ERR_BADREG (-6) /* Bad register number */
extern int pci_initialize();
typedef struct {
volatile unsigned char* pci_config_addr;
@@ -1112,45 +1131,79 @@ typedef struct {
extern pci_config BSP_pci_configuration;
extern inline int
pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function,
unsigned char where, unsigned char * val) {
return BSP_pci_configuration.pci_functions->read_config_byte(bus, slot, function, where, val);
pci_read_config_byte(
unsigned char bus,
unsigned char slot,
unsigned char function,
unsigned char where,
unsigned char * val)
{
return BSP_pci_configuration.pci_functions->read_config_byte(
bus, slot, function, where, val);
}
extern inline int
pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function,
unsigned char where, unsigned short * val) {
return BSP_pci_configuration.pci_functions->read_config_word(bus, slot, function, where, val);
pci_read_config_word(
unsigned char bus,
unsigned char slot,
unsigned char function,
unsigned char where,
unsigned short * val)
{
return BSP_pci_configuration.pci_functions->read_config_word(
bus, slot, function, where, val);
}
extern inline int
pci_read_config_dword(unsigned char bus, unsigned char slot, unsigned char function,
unsigned char where, unsigned int * val) {
pci_read_config_dword(
unsigned char bus,
unsigned char slot,
unsigned char function,
unsigned char where,
unsigned int * val)
{
return BSP_pci_configuration.pci_functions->read_config_dword(bus, slot, function, where, val);
}
extern inline int
pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function,
unsigned char where, unsigned char val) {
return BSP_pci_configuration.pci_functions->write_config_byte(bus, slot, function, where, val);
pci_write_config_byte(
unsigned char bus,
unsigned char slot,
unsigned char function,
unsigned char where,
unsigned char val)
{
return BSP_pci_configuration.pci_functions->write_config_byte(
bus, slot, function, where, val);
}
extern inline int
pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function,
unsigned char where, unsigned short val) {
return BSP_pci_configuration.pci_functions->write_config_word(bus, slot, function, where, val);
pci_write_config_word(
unsigned char bus,
unsigned char slot,
unsigned char function,
unsigned char where,
unsigned short val)
{
return BSP_pci_configuration.pci_functions->write_config_word(
bus, slot, function, where, val);
}
extern inline int
pci_write_config_dword(unsigned char bus, unsigned char slot, unsigned char function,
unsigned char where, unsigned int val) {
return BSP_pci_configuration.pci_functions->write_config_dword(bus, slot, function, where, val);
pci_write_config_dword(
unsigned char bus,
unsigned char slot,
unsigned char function,
unsigned char where,
unsigned int val)
{
return BSP_pci_configuration.pci_functions->write_config_dword(
bus, slot, function, where, val);
}
/*
* Return the number of PCI busses in the system
*/
extern unsigned char BusCountPCI();
extern void InitializePCI();
#endif /* _RTEMS_PCI_H */