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sparc: Optimize context switch

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The registers g2 through g4 are reserved for applications.  GCC uses
them as volatile registers by default.  So they are treated like
volatile registers in RTEMS as well.
This commit is contained in:
Sebastian Huber
2014-04-22 07:46:56 +02:00
parent e5120a566c
commit b2ec2d1597
4 changed files with 53 additions and 55 deletions
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doc/cpu_supplement/sparc.t
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@@ -397,6 +397,9 @@ describes the role of each of these registers:
@end html
@end ifset
The registers g2 through g4 are reserved for applications. GCC uses them as
volatile registers by default. So they are treated like volatile registers in
RTEMS as well.
@subsubsection Floating Point Registers