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sparc: Optimize context switch

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The registers g2 through g4 are reserved for applications.  GCC uses
them as volatile registers by default.  So they are treated like
volatile registers in RTEMS as well.
This commit is contained in:
Sebastian Huber
2014-04-22 07:46:56 +02:00
parent e5120a566c
commit b2ec2d1597
4 changed files with 53 additions and 55 deletions
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6
c/src/lib/libbsp/sparc/shared/irq_asm.S
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@@ -52,8 +52,7 @@
.align 4
PUBLIC(_CPU_Context_switch)
SYM(_CPU_Context_switch):
std %g2, [%o0 + G2_OFFSET] ! save the global registers
std %g4, [%o0 + G4_OFFSET]
st %g5, [%o0 + G5_OFFSET] ! save the global registers
std %g6, [%o0 + G6_OFFSET]
std %l0, [%o0 + L0_OFFSET] ! save the local registers
@@ -185,8 +184,7 @@ done_flushing:
nop
nop
ldd [%o1 + G2_OFFSET], %g2 ! restore the global registers
ldd [%o1 + G4_OFFSET], %g4
ld [%o1 + G5_OFFSET], %g5 ! restore the global registers
ldd [%o1 + G6_OFFSET], %g6
! Load thread specific ISR dispatch prevention flag