forked from Imagelibrary/rtems
2007-06-22 Joel Sherrill <joel.sherrill@oarcorp.com>
* clock/clock.c, network_5200/network.c: Convert to using clock driver template.
This commit is contained in:
@@ -1,3 +1,8 @@
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2007-06-22 Joel Sherrill <joel.sherrill@oarcorp.com>
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* clock/clock.c, network_5200/network.c: Convert to using clock driver
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template.
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2007-06-22 Joel Sherrill <joel.sherrill@OARcorp.com>
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2007-06-22 Joel Sherrill <joel.sherrill@OARcorp.com>
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* startup/linkcmds.brs5l: Add missing wild card on .sdata section so
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* startup/linkcmds.brs5l: Add missing wild card on .sdata section so
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@@ -10,6 +10,8 @@
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| D-82178 Puchheim |
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| D-82178 Puchheim |
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| Germany |
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| Germany |
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| rtems@embedded-brains.de |
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| rtems@embedded-brains.de |
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| |
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| Reworked by Joel Sherrill to use clockdrv_shell.c |
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+-----------------------------------------------------------------+
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+-----------------------------------------------------------------+
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| The license and distribution terms for this file may be |
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| The license and distribution terms for this file may be |
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| found in the file LICENSE in this distribution or at |
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| found in the file LICENSE in this distribution or at |
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@@ -110,75 +112,58 @@
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#include <stdlib.h> /* for atexit() */
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#include <stdlib.h> /* for atexit() */
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#include "../include/mpc5200.h"
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#include "../include/mpc5200.h"
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volatile uint32_t Clock_driver_ticks;
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#define GPT (BSP_PERIODIC_TIMER - BSP_SIU_IRQ_TMR0)
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void Clock_exit(void);
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uint32_t counter_value;
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volatile int ClockInitialized = 0;
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/*
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* These are set by clock driver during its init
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*/
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rtems_device_major_number rtems_clock_major = ~0;
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rtems_device_minor_number rtems_clock_minor;
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/* this lets us do nanoseconds since last tick */
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uint64_t Clock_last_TBR;
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uint64_t Clock_last_TBR;
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volatile uint32_t counter_value;
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volatile int ClockInitialized = 0;
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/*
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/*
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* ISR Handlers
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* ISR Handlers
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*/
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*/
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void mpc5200_gpt_clock_isr(rtems_irq_hdl_param handle)
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void mpc5200_gpt_clock_isr(rtems_irq_hdl_param handle)
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{
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{
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uint32_t status;
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uint32_t status;
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)handle;
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)handle;
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status = gpt->status;
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status = gpt->status;
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if (ClockInitialized && (status & GPT_STATUS_TEXP)) {
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if(ClockInitialized && (status & GPT_STATUS_TEXP))
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{
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gpt->status |= GPT_STATUS_TEXP;
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gpt->status |= GPT_STATUS_TEXP;
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Clock_last_TBR = PPC_Get_timebase_register();
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Clock_last_TBR = PPC_Get_timebase_register();
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Clock_driver_ticks++;
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Clock_driver_ticks++;
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rtems_clock_tick();
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rtems_clock_tick();
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}
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}
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}
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}
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/*
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/*
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* Initialize MPC5x00 GPT
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* Initialize MPC5x00 GPT
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*/
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*/
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void mpc5200_init_gpt(uint32_t gpt_no)
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void mpc5200_init_gpt(uint32_t gpt_no)
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{
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{
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]);
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]);
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gpt->status = GPT_STATUS_RESET;
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gpt->status = GPT_STATUS_RESET;
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gpt->emsel = GPT_EMSEL_CE | GPT_EMSEL_ST_CONT | GPT_EMSEL_INTEN | GPT_EMSEL_GPIO_OUT_HIGH | GPT_EMSEL_TIMER_MS_GPIO;
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gpt->emsel = GPT_EMSEL_CE | GPT_EMSEL_ST_CONT | GPT_EMSEL_INTEN |
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GPT_EMSEL_GPIO_OUT_HIGH | GPT_EMSEL_TIMER_MS_GPIO;
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}
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}
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/*
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/*
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* Set MPC5x00 GPT counter
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* Set MPC5x00 GPT counter
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*/
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*/
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void mpc5200_set_gpt_count(uint32_t counter_value, uint32_t gpt_no)
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void mpc5200_set_gpt_count(uint32_t counter_value, uint32_t gpt_no)
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{
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{
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uint32_t prescaler_value = 1;
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uint32_t prescaler_value = 1;
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uint32_t counter = counter_value;
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uint32_t counter = counter_value;
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]);
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]);
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/* Calculate counter/prescaler value, e.g. IPB_Clock=33MHz -> Int. every 0,3 nsecs. - 130 secs.*/
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/* Calculate counter/prescaler value, e.g.
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while((counter >= (1 << 16)) && (prescaler_value < (1 << 16)))
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* IPB_Clock=33MHz -> Int. every 0,3 nsecs. - 130 secs
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{
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*/
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while ((counter >= (1 << 16)) && (prescaler_value < (1 << 16))) {
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prescaler_value++;
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prescaler_value++;
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counter = counter_value / prescaler_value;
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counter = counter_value / prescaler_value;
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}
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}
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@@ -187,7 +172,7 @@ void mpc5200_set_gpt_count(uint32_t counter_value, uint32_t gpt_no)
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gpt->count_in = (prescaler_value << 16) + counter;
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gpt->count_in = (prescaler_value << 16) + counter;
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}
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}
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uint32_t bsp_clock_nanoseconds_since_last_tick(void)
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uint32_t bsp_clock_nanoseconds_since_last_tick(void)
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{
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{
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@@ -206,41 +191,35 @@ uint32_t bsp_clock_nanoseconds_since_last_tick(void)
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* Enable MPC5x00 GPT interrupt
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* Enable MPC5x00 GPT interrupt
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*/
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*/
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void mpc5200_enable_gpt_int(uint32_t gpt_no)
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void mpc5200_enable_gpt_int(uint32_t gpt_no)
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{
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{
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]);
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]);
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gpt->emsel |= GPT_EMSEL_CE | GPT_EMSEL_INTEN;
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gpt->emsel |= GPT_EMSEL_CE | GPT_EMSEL_INTEN;
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Clock_last_TBR = PPC_Get_timebase_register();
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Clock_last_TBR = PPC_Get_timebase_register();
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}
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}
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/*
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/*
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* Disable MPC5x00 GPT interrupt
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* Disable MPC5x00 GPT interrupt
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*/
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*/
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void mpc5200_disable_gpt_int(uint32_t gpt_no)
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void mpc5200_disable_gpt_int(uint32_t gpt_no)
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{
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{
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]);
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]);
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gpt->emsel &= ~(GPT_EMSEL_CE | GPT_EMSEL_INTEN);
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gpt->emsel &= ~(GPT_EMSEL_CE | GPT_EMSEL_INTEN);
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}
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}
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/*
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/*
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* Check MPC5x00 GPT status
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* Check MPC5x00 GPT status
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*/
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*/
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uint32_t mpc5200_check_gpt_status(uint32_t gpt_no)
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uint32_t mpc5200_check_gpt_status(uint32_t gpt_no)
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{
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{
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]);
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struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]);
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return ((gpt->emsel) & (GPT_EMSEL_CE | GPT_EMSEL_INTEN));
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return ((gpt->emsel) & (GPT_EMSEL_CE | GPT_EMSEL_INTEN));
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}
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}
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void clockOn(const rtems_irq_connect_data* irq)
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void clockOn(const rtems_irq_connect_data* irq)
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{
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{
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uint32_t gpt_no;
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uint32_t gpt_no;
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gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
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gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
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@@ -251,14 +230,11 @@ void clockOn(const rtems_irq_connect_data* irq)
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mpc5200_set_gpt_count(counter_value, (uint32_t)gpt_no);
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mpc5200_set_gpt_count(counter_value, (uint32_t)gpt_no);
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mpc5200_enable_gpt_int((uint32_t)gpt_no);
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mpc5200_enable_gpt_int((uint32_t)gpt_no);
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Clock_driver_ticks = 0;
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ClockInitialized = 1;
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ClockInitialized = 1;
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}
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}
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void clockOff(const rtems_irq_connect_data* irq)
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void clockOff(const rtems_irq_connect_data* irq)
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{
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{
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uint32_t gpt_no;
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uint32_t gpt_no;
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gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
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gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
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@@ -266,87 +242,68 @@ void clockOff(const rtems_irq_connect_data* irq)
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mpc5200_disable_gpt_int((uint32_t)gpt_no);
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mpc5200_disable_gpt_int((uint32_t)gpt_no);
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ClockInitialized = 0;
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ClockInitialized = 0;
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}
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}
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int clockIsOn(const rtems_irq_connect_data* irq)
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int clockIsOn(const rtems_irq_connect_data* irq)
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{
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{
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uint32_t gpt_no;
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uint32_t gpt_no;
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gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
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gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
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if(mpc5200_check_gpt_status(gpt_no) && ClockInitialized)
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if (mpc5200_check_gpt_status(gpt_no) && ClockInitialized)
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return ClockInitialized;
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return ClockInitialized;
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else
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return 0;
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return 0;
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}
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}
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int BSP_get_clock_irq_level()
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int BSP_get_clock_irq_level()
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{
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{
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/*
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/*
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* Caution : if you change this, you must change the
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* Caution : if you change this, you must change the
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* definition of BSP_PERIODIC_TIMER accordingly
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* definition of BSP_PERIODIC_TIMER accordingly
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*/
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*/
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return BSP_PERIODIC_TIMER;
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return BSP_PERIODIC_TIMER;
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}
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}
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int BSP_disconnect_clock_handler (void)
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int BSP_disconnect_clock_handler (void)
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{
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{
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rtems_irq_connect_data clockIrqData;
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rtems_irq_connect_data clockIrqData;
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clockIrqData.name = BSP_PERIODIC_TIMER;
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clockIrqData.name = BSP_PERIODIC_TIMER;
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if (!BSP_get_current_rtems_irq_handler(&clockIrqData))
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if (!BSP_get_current_rtems_irq_handler(&clockIrqData)) {
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{
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printk("Unable to stop system clock\n");
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printk("Unable to stop system clock\n");
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rtems_fatal_error_occurred(1);
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rtems_fatal_error_occurred(1);
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}
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}
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return BSP_remove_rtems_irq_handler (&clockIrqData);
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return BSP_remove_rtems_irq_handler (&clockIrqData);
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}
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}
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int BSP_connect_clock_handler (uint32_t gpt_no)
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int BSP_connect_clock_handler (uint32_t gpt_no)
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{
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{
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rtems_irq_hdl hdl = 0;
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rtems_irq_hdl hdl = 0;
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rtems_irq_connect_data clockIrqData;
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rtems_irq_connect_data clockIrqData;
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/*
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/*
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* Reinit structure
|
* Reinit structure
|
||||||
*/
|
*/
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|
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clockIrqData.name = BSP_PERIODIC_TIMER;
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clockIrqData.name = BSP_PERIODIC_TIMER;
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if(!BSP_get_current_rtems_irq_handler(&clockIrqData))
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if (!BSP_get_current_rtems_irq_handler(&clockIrqData)) {
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{
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|
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printk("Unable to get system clock handler\n");
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printk("Unable to get system clock handler\n");
|
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rtems_fatal_error_occurred(1);
|
rtems_fatal_error_occurred(1);
|
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|
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}
|
}
|
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|
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if(!BSP_remove_rtems_irq_handler (&clockIrqData))
|
if (!BSP_remove_rtems_irq_handler (&clockIrqData)) {
|
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{
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|
||||||
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|
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printk("Unable to remove current system clock handler\n");
|
printk("Unable to remove current system clock handler\n");
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rtems_fatal_error_occurred(1);
|
rtems_fatal_error_occurred(1);
|
||||||
|
|
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}
|
}
|
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|
||||||
if ((gpt_no >= GPT0) ||
|
if ((gpt_no >= GPT0) || (gpt_no <= GPT7)) {
|
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(gpt_no <= GPT7)) {
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|
||||||
hdl = (rtems_irq_hdl_param )&mpc5200.gpt[gpt_no];
|
hdl = (rtems_irq_hdl_param )&mpc5200.gpt[gpt_no];
|
||||||
}
|
} else {
|
||||||
else {
|
|
||||||
printk("Unable to set system clock handler\n");
|
printk("Unable to set system clock handler\n");
|
||||||
rtems_fatal_error_occurred(1);
|
rtems_fatal_error_occurred(1);
|
||||||
}
|
}
|
||||||
@@ -358,106 +315,42 @@ int BSP_connect_clock_handler (uint32_t gpt_no)
|
|||||||
clockIrqData.isOn = clockIsOn;
|
clockIrqData.isOn = clockIsOn;
|
||||||
|
|
||||||
return BSP_install_rtems_irq_handler (&clockIrqData);
|
return BSP_install_rtems_irq_handler (&clockIrqData);
|
||||||
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|
||||||
}
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|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Called via atexit()
|
|
||||||
* Remove the clock interrupt handler by setting handler to NULL
|
|
||||||
*/
|
|
||||||
void Clock_exit(void)
|
|
||||||
{
|
|
||||||
|
|
||||||
(void) BSP_disconnect_clock_handler ();
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|
||||||
|
|
||||||
}
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|
||||||
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|
||||||
|
|
||||||
void Install_clock(rtems_device_minor_number gpt_no)
|
|
||||||
{
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|
||||||
|
|
||||||
Clock_driver_ticks = 0;
|
|
||||||
|
|
||||||
counter_value = rtems_configuration_get_microseconds_per_tick() *
|
|
||||||
rtems_cpu_configuration_get_clicks_per_usec();
|
|
||||||
|
|
||||||
mpc5200_init_gpt((uint32_t)gpt_no);
|
|
||||||
mpc5200_set_gpt_count(counter_value, (uint32_t)gpt_no);
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|
||||||
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|
||||||
|
|
||||||
BSP_connect_clock_handler(gpt_no);
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|
||||||
|
|
||||||
ClockInitialized = 1;
|
|
||||||
|
|
||||||
rtems_clock_set_nanoseconds_extension(
|
|
||||||
bsp_clock_nanoseconds_since_last_tick
|
|
||||||
);
|
|
||||||
atexit(Clock_exit);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
void ReInstall_clock(uint32_t gpt_no)
|
|
||||||
{
|
|
||||||
|
|
||||||
BSP_connect_clock_handler(gpt_no);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
rtems_device_driver Clock_initialize
|
|
||||||
(
|
|
||||||
rtems_device_major_number major,
|
|
||||||
rtems_device_minor_number minor,
|
|
||||||
void *pargp
|
|
||||||
)
|
|
||||||
{
|
|
||||||
/* force minor according to definitions in irq.h */
|
|
||||||
minor = BSP_PERIODIC_TIMER - BSP_SIU_IRQ_TMR0;
|
|
||||||
|
|
||||||
Install_clock((uint32_t)minor);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* make major/minor avail to others such as shared memory driver
|
|
||||||
*/
|
|
||||||
rtems_clock_major = major;
|
|
||||||
rtems_clock_minor = minor;
|
|
||||||
|
|
||||||
return RTEMS_SUCCESSFUL;
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
rtems_device_driver Clock_control
|
|
||||||
(
|
|
||||||
rtems_device_major_number major,
|
|
||||||
rtems_device_minor_number minor,
|
|
||||||
void *pargp
|
|
||||||
) {
|
|
||||||
|
|
||||||
rtems_libio_ioctl_args_t *args = pargp;
|
|
||||||
|
|
||||||
/* forec minor according to definitions in irq.h */
|
|
||||||
minor = BSP_PERIODIC_TIMER - BSP_SIU_IRQ_TMR0;
|
|
||||||
|
|
||||||
if(args != 0) {
|
|
||||||
/*
|
|
||||||
* This is hokey, but until we get a defined interface
|
|
||||||
* to do this, it will just be this simple...
|
|
||||||
*/
|
|
||||||
if(args->command == rtems_build_name('I', 'S', 'R', ' ')) {
|
|
||||||
if ((minor >= GPT0) ||
|
|
||||||
(minor <= GPT7)) {
|
|
||||||
mpc5200_gpt_clock_isr((rtems_irq_hdl_param )&mpc5200.gpt[minor]);
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
printk("Unable to call system clock handler\n");
|
|
||||||
rtems_fatal_error_occurred(1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else if(args->command == rtems_build_name('N', 'E', 'W', ' ')) {
|
|
||||||
ReInstall_clock((uint32_t)minor);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return RTEMS_SUCCESSFUL;
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#define CLOCK_VECTOR 0
|
||||||
|
|
||||||
|
#define Clock_driver_support_at_tick() \
|
||||||
|
do { \
|
||||||
|
uint32_t status; \
|
||||||
|
struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[GPT]); \
|
||||||
|
\
|
||||||
|
status = gpt->status; \
|
||||||
|
\
|
||||||
|
if (ClockInitialized && (status & GPT_STATUS_TEXP)) { \
|
||||||
|
gpt->status |= GPT_STATUS_TEXP; \
|
||||||
|
Clock_last_TBR = PPC_Get_timebase_register(); \
|
||||||
|
} \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define Clock_driver_support_install_isr( _new, _old ) \
|
||||||
|
do { \
|
||||||
|
(_old) = NULL; /* avoid warning */; \
|
||||||
|
BSP_connect_clock_handler(GPT); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
/* This driver does this in clockOn called at connection time */
|
||||||
|
#define Clock_driver_support_initialize_hardware() \
|
||||||
|
do { \
|
||||||
|
; \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
|
#define Clock_driver_nanoseconds_since_last_tick \
|
||||||
|
bsp_clock_nanoseconds_since_last_tick
|
||||||
|
|
||||||
|
#define Clock_driver_support_shutdown_hardware() \
|
||||||
|
do { \
|
||||||
|
(void) BSP_disconnect_clock_handler (); \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
|
#include "../../../shared/clockdrv_shell.c"
|
||||||
|
|
||||||
|
|||||||
@@ -103,7 +103,7 @@ extern TaskBDIdxTable_t TaskBDIdxTable[MAX_TASKS];
|
|||||||
static TaskId rxTaskId; /* SDMA RX task ID */
|
static TaskId rxTaskId; /* SDMA RX task ID */
|
||||||
static TaskId txTaskId; /* SDMA TX task ID */
|
static TaskId txTaskId; /* SDMA TX task ID */
|
||||||
|
|
||||||
/*#define ETH_DEBUG*/
|
#define ETH_DEBUG
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Number of interfaces supported by this driver
|
* Number of interfaces supported by this driver
|
||||||
@@ -565,6 +565,7 @@ void mpc5200_fec_off(struct mpc5200_enet_struct *sc)
|
|||||||
{
|
{
|
||||||
int counter = 0xffff;
|
int counter = 0xffff;
|
||||||
|
|
||||||
|
|
||||||
#if defined(ETH_DEBUG)
|
#if defined(ETH_DEBUG)
|
||||||
unsigned short phyStatus, i;
|
unsigned short phyStatus, i;
|
||||||
unsigned char phyAddr = 0;
|
unsigned char phyAddr = 0;
|
||||||
@@ -1241,6 +1242,7 @@ static void mpc5200_fec_initialize_phy(struct mpc5200_enet_struct *sc)
|
|||||||
|
|
||||||
#if defined(ETH_DEBUG)
|
#if defined(ETH_DEBUG)
|
||||||
int i;
|
int i;
|
||||||
|
unsigned short phyStatus;
|
||||||
/*
|
/*
|
||||||
* Print PHY registers after initialization.
|
* Print PHY registers after initialization.
|
||||||
*/
|
*/
|
||||||
|
|||||||
Reference in New Issue
Block a user