bsp/altera-cyclone-v: Use FDT for clock frequency

This commit is contained in:
Sebastian Huber
2019-02-18 08:24:37 +01:00
parent 43fbb50ff0
commit af80b0a340
3 changed files with 15 additions and 3 deletions

View File

@@ -43,6 +43,12 @@ extern "C" {
#define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 )
#ifndef BSP_ARM_A9MPCORE_PERIPHCLK
extern uint32_t altera_cyclone_v_a9mpcore_periphclk;
#define BSP_ARM_A9MPCORE_PERIPHCLK altera_cyclone_v_a9mpcore_periphclk
#define ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK
#endif
#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
#define BSP_ARM_L2C_310_BASE 0xfffef000

View File

@@ -93,10 +93,17 @@ static void update_clocks(void)
}
#endif
#ifdef ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK
uint32_t altera_cyclone_v_a9mpcore_periphclk;
#endif
void bsp_start(void)
{
#ifdef BSP_FDT_IS_SUPPORTED
update_clocks();
#endif
#ifdef ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK
alt_clk_freq_get(ALT_CLK_MPU_PERIPH, &altera_cyclone_v_a9mpcore_periphclk);
#endif
bsp_interrupt_initialize();
rtems_cache_coherent_add_area(