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2010-04-28 Joel Sherrill <joel.sherrilL@OARcorp.com>

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* irq/irq.h, startup/iss555.c, startup/tm27supp.c: Remove warnings.
This commit is contained in:
Joel Sherrill
2010-04-28 17:17:48 +00:00
parent 6196ded1d5
commit af2af2b4b7
4 changed files with 21 additions and 18 deletions
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4
c/src/lib/libbsp/powerpc/ss555/ChangeLog
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@@ -1,3 +1,7 @@
2010-04-28 Joel Sherrill <joel.sherrilL@OARcorp.com>
* irq/irq.h, startup/iss555.c, startup/tm27supp.c: Remove warnings.
2010-03-27 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> 2010-03-27 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* startup/start.S: remove bootcard calling warning * startup/start.S: remove bootcard calling warning

12
c/src/lib/libbsp/powerpc/ss555/irq/irq.h
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@@ -35,6 +35,18 @@
extern "C" { extern "C" {
#endif #endif
/*
* These are no longer prototyped anywhere else. This appears to be
* remnants of the IRQ code upgrade.
*
* --joel 28 April 2010
*/
int CPU_install_rtems_irq_handler(const rtems_irq_connect_data* irq);
int CPU_get_current_rtems_irq_handler(rtems_irq_connect_data* irq);
int CPU_remove_rtems_irq_handler(const rtems_irq_connect_data* irq);
int CPU_rtems_irq_mngt_set(rtems_irq_global_settings* config);
int CPU_rtems_irq_mngt_get(rtems_irq_global_settings** config);
/* /*
* The SS555 has no external interrupt controller chip, so use the standard * The SS555 has no external interrupt controller chip, so use the standard
* routines from the CPU-dependent code. * routines from the CPU-dependent code.

4
c/src/lib/libbsp/powerpc/ss555/startup/iss555.c
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@@ -26,6 +26,8 @@ SPR_RW(MI_GRA);
SPR_RW(L2U_GRA); SPR_RW(L2U_GRA);
SPR_RW(BBCMCR); SPR_RW(BBCMCR);
extern char int_ram_top[]; /* top of internal ram */
/* /*
* Initialize SS555 * Initialize SS555
*/ */
@@ -94,8 +96,6 @@ void _InitSS555 (void)
* extend the internal RAM. If booting from external RAM, leave it at * extend the internal RAM. If booting from external RAM, leave it at
* zero but set it up appropriately. * zero but set it up appropriately.
*/ */
extern char int_ram_top[]; /* top of internal ram */
usiu.memc[0]._or = usiu.memc[0]._or =
USIU_MEMC_OR_512K /* bank size */ USIU_MEMC_OR_512K /* bank size */
| USIU_MEMC_OR_SCY(0) /* wait states in first beat of burst */ | USIU_MEMC_OR_SCY(0) /* wait states in first beat of burst */

19
c/src/lib/libbsp/powerpc/ss555/startup/tm27supp.c
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@@ -6,24 +6,11 @@
#include <bsp.h> #include <bsp.h>
void tm27On(void)
{
}
void tm27Off(void)
{
}
int tm27IsOn(void)
{
return 1;
}
rtems_irq_connect_data tm27IrqData = { rtems_irq_connect_data tm27IrqData = {
CPU_USIU_EXT_IRQ_7, CPU_USIU_EXT_IRQ_7,
(rtems_irq_hdl)0, (rtems_irq_hdl)0,
(rtems_irq_enable)tm27On, NULL,
(rtems_irq_disable)tm27Off, NULL,
(rtems_irq_is_enabled)tm27IsOn NULL
}; };