forked from Imagelibrary/rtems
2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
* new-exceptions/cpu_asm.S: Use BSP_DATA_CACHE_ENABLED instead of PPC_USE_DATA_CACHE.
This commit is contained in:
@@ -1,3 +1,8 @@
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2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* new-exceptions/cpu_asm.S: Use BSP_DATA_CACHE_ENABLED instead of
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PPC_USE_DATA_CACHE.
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2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* shared/src/cache_.h: Moved implementation from "cache.c" to here.
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@@ -293,21 +293,21 @@ PROC (_CPU_Context_switch):
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sync
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isync
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/* This assumes that all the registers are in the given order */
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#if ( PPC_USE_DATA_CACHE )
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#if ( BSP_DATA_CACHE_ENABLED )
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#if PPC_CACHE_ALIGNMENT != 32
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#error "code assumes PPC_CACHE_ALIGNMENT == 32!"
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#endif
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li r5, PPC_CACHE_ALIGNMENT
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#endif
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addi r9,r3,-4
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#if ( PPC_USE_DATA_CACHE )
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#if ( BSP_DATA_CACHE_ENABLED )
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dcbz r5, r9
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#endif
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stw r1, GP_1+4(r9)
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stw r2, GP_2+4(r9)
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#if (PPC_USE_MULTIPLE == 1)
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addi r9, r9, GP_18+4
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#if ( PPC_USE_DATA_CACHE )
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#if ( BSP_DATA_CACHE_ENABLED )
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dcbz r5, r9
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#endif
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stmw r13, GP_13-GP_18(r9)
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@@ -318,7 +318,7 @@ PROC (_CPU_Context_switch):
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stw r16, GP_16+4(r9)
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stw r17, GP_17+4(r9)
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stwu r18, GP_18+4(r9)
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#if ( PPC_USE_DATA_CACHE )
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#if ( BSP_DATA_CACHE_ENABLED )
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dcbz r5, r9
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#endif
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stw r19, GP_19-GP_18(r9)
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@@ -335,7 +335,7 @@ PROC (_CPU_Context_switch):
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stw r30, GP_30-GP_18(r9)
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stw r31, GP_31-GP_18(r9)
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#endif
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#if ( PPC_USE_DATA_CACHE )
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#if ( BSP_DATA_CACHE_ENABLED )
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dcbt r0, r4
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#endif
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mfcr r6
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@@ -350,19 +350,19 @@ PROC (_CPU_Context_switch):
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EXTERN_PROC(_CPU_Context_switch_altivec)
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bl _CPU_Context_switch_altivec
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mr r4, r14
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#if ( PPC_USE_DATA_CACHE )
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#if ( BSP_DATA_CACHE_ENABLED )
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li r5, PPC_CACHE_ALIGNMENT
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#endif
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#endif
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#if ( PPC_USE_DATA_CACHE )
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#if ( BSP_DATA_CACHE_ENABLED )
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dcbt r5, r4
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#endif
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lwz r1, GP_1(r4)
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lwz r2, GP_2(r4)
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#if (PPC_USE_MULTIPLE == 1)
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addi r4, r4, GP_19
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#if ( PPC_USE_DATA_CACHE )
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#if ( BSP_DATA_CACHE_ENABLED )
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dcbt r5, r4
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#endif
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lmw r13, GP_13-GP_19(r4)
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@@ -374,7 +374,7 @@ PROC (_CPU_Context_switch):
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lwz r17, GP_17(r4)
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lwz r18, GP_18(r4)
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lwzu r19, GP_19(r4)
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#if ( PPC_USE_DATA_CACHE )
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#if ( BSP_DATA_CACHE_ENABLED )
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dcbt r5, r4
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#endif
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lwz r20, GP_20-GP_19(r4)
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