forked from Imagelibrary/rtems
bsps/stm32h7: remove external memory initialization from nucleo-h743zi BSP
Nucleo board does not provide any external memory so code does not have any function here anyway. Sponsored-By: Precidata
This commit is contained in:
Karel Gardas
@@ -1,478 +0,0 @@
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/**
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******************************************************************************
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* @file system_stm32h7xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32h7xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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#include <stm32h7xx_hal.h>
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#define DATA_IN_ExtSRAM
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#define DATA_IN_ExtSDRAM
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void SystemInit_ExtMemCtl(void)
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{
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#define FMC_BMAP_Value 0x02000000 /* FMC Bank Mapping 2 (SDRAM Bank2 remapped) */
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__IO uint32_t tmp = 0;
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/********** SDRAM + SRAM ***********************************************************************/
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#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
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register uint32_t tmpreg = 0, timeout = 0xFFFF;
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register __IO uint32_t index;
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/*-- I/O Ports Configuration ------------------------------------------------------*/
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/* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
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RCC->AHB4ENR |= 0x000001F8;
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/* Delay after an RCC peripheral clock enabling */
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tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);
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/* Connect PDx pins to FMC Alternate function */
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GPIOD->AFR[0] = 0x00CC00CC;
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GPIOD->AFR[1] = 0xCCCCCCCC;
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/* Configure PDx pins in Alternate function mode */
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GPIOD->MODER = 0xAAAAFAFA;
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/* Configure PDx pins speed to 100 MHz */
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GPIOD->OSPEEDR = 0xFFFF0F0F;
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/* Configure PDx pins Output type to push-pull */
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GPIOD->OTYPER = 0x00000000;
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/* Configure PDx pins in Pull-up */
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GPIOD->PUPDR = 0x55550505;
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/* Connect PEx pins to FMC Alternate function */
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GPIOE->AFR[0] = 0xC00CC0CC;
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GPIOE->AFR[1] = 0xCCCCCCCC;
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/* Configure PEx pins in Alternate function mode */
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GPIOE->MODER = 0xAAAABEBA;
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/* Configure PEx pins speed to 100 MHz */
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GPIOE->OSPEEDR = 0xFFFFC3CF;
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/* Configure PEx pins Output type to push-pull */
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GPIOE->OTYPER = 0x00000000;
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/* Configure PEx pins in Pull-up */
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GPIOE->PUPDR = 0x55554145;
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/* Connect PFx pins to FMC Alternate function */
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GPIOF->AFR[0] = 0x00CCCCCC;
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GPIOF->AFR[1] = 0xCCCCC000;
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/* Configure PFx pins in Alternate function mode */
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GPIOF->MODER = 0xAABFFAAA;
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/* Configure PFx pins speed to 100 MHz */
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GPIOF->OSPEEDR = 0xFFC00FFF;
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/* Configure PFx pins Output type to push-pull */
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GPIOF->OTYPER = 0x00000000;
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/* Configure PFx pins in Pull-up */
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GPIOF->PUPDR = 0x55400555;
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/* Connect PGx pins to FMC Alternate function */
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GPIOG->AFR[0] = 0x00CCCCCC;
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GPIOG->AFR[1] = 0xC0000C0C;
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/* Configure PGx pins in Alternate function mode */
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GPIOG->MODER = 0xBFEEFAAA;
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/* Configure PGx pins speed to 100 MHz */
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GPIOG->OSPEEDR = 0xC0330FFF;
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/* Configure PGx pins Output type to push-pull */
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GPIOG->OTYPER = 0x00000000;
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/* Configure PGx pins in Pull-up */
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GPIOG->PUPDR = 0x40110555;
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/* Connect PHx pins to FMC Alternate function */
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GPIOH->AFR[0] = 0xCCC00000;
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GPIOH->AFR[1] = 0xCCCCCCCC;
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/* Configure PHx pins in Alternate function mode */
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GPIOH->MODER = 0xAAAAABFF;
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/* Configure PHx pins speed to 100 MHz */
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GPIOH->OSPEEDR = 0xFFFFFC00;
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/* Configure PHx pins Output type to push-pull */
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GPIOH->OTYPER = 0x00000000;
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/* Configure PHx pins in Pull-up */
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GPIOH->PUPDR = 0x55555400;
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/* Connect PIx pins to FMC Alternate function */
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GPIOI->AFR[0] = 0xCCCCCCCC;
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GPIOI->AFR[1] = 0x00000CC0;
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/* Configure PIx pins in Alternate function mode */
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GPIOI->MODER = 0xFFEBAAAA;
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/* Configure PIx pins speed to 100 MHz */
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GPIOI->OSPEEDR = 0x003CFFFF;
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/* Configure PIx pins Output type to push-pull */
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GPIOI->OTYPER = 0x00000000;
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/* Configure PIx pins in Pull-up */
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GPIOI->PUPDR = 0x00145555;
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/*-- FMC Configuration ------------------------------------------------------*/
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/* Enable the FMC/FSMC interface clock */
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(RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
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/* Configure and enable Bank1_SRAM2 */
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FMC_Bank1_R->BTCR[4] = 0x00001091;
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FMC_Bank1_R->BTCR[5] = 0x00110212;
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FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
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/* SDRAM Timing and access interface configuration */
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/*SDBank = FMC_SDRAM_BANK2
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ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9 CC
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RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12 RR
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MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32 MM
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InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4 N
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CASLatency = FMC_SDRAM_CAS_LATENCY_2 LL // 2 oder 3, s.u.
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WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE W
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SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2 KK
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ReadBurst = FMC_SDRAM_RBURST_ENABLE B
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ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0 PP
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LoadToActiveDelay = 2 -> 1 LLLL TMRD
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ExitSelfRefreshDelay = 6 -> 5 EEEE TXSR
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SelfRefreshTime = 4 -> 3 SSSS TRAS
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RowCycleDelay = 6 -> 5 RRRR TRC
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WriteRecoveryTime = 2 -> 1 WWWW TWR
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RPDelay = 2 -> 1 PPPP TRP
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RCDDelay = 2 -> 1 CCCC TRCD */
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#if 0
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FMC_Bank5_6_R->SDCR[0] = 0x00005965; // 0000 0000 0000 0000 0101 1001 0110 0101 Bank 1
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// PPB KKWL LNMM RRCC
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FMC_Bank5_6_R->SDCR[1] = 0x00005965; // 0000 0000 0000 0000 0101 1001 0110 0101 Bank 2 // CAS Latency = 2
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// WL LNMM RRCC
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FMC_Bank5_6_R->SDTR[0] = 0x00105000; // 0000 0000 0001 0000 0101 0000 0000 0000 Bank 1 // Original,
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// CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 2 (s.o.)
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FMC_Bank5_6_R->SDTR[1] = 0x01010351; // 0000 0001 0000 0001 0000 0011 0101 0001 Bank 2
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// CCCC WWWW SSSS EEEE LLLL
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#endif
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#if 0
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FMC_Bank5_6_R->SDTR[0] = 0x00206000; // 0000 0000 0010 0000 0110 0000 0000 0000 Bank 1 // Original + 1 bei allen Werten,
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// CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 3 (s.o.)
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FMC_Bank5_6_R->SDTR[1] = 0x02020462; // 0000 0010 0000 0010 0000 0100 0110 0010 Bank 2
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// CCCC WWWW SSSS EEEE LLLL
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#endif
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#if 0
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FMC_Bank5_6_R->SDTR[0] = 0x00209000; // 0000 0000 0010 0000 1001 0000 0000 0000 Bank 1 // Versuch anhand ISSI-Datenblatt,
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// CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 3 (s.o.)
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FMC_Bank5_6_R->SDTR[1] = 0x020306B1; // 0000 0010 0000 0011 0000 0110 1011 0001 Bank 2
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// CCCC WWWW SSSS EEEE LLLL
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#endif
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FMC_Bank5_6_R->SDCR[0] = 0x00001800;
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FMC_Bank5_6_R->SDCR[1] = 0x00000165;
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FMC_Bank5_6_R->SDTR[0] = 0x00105000;
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FMC_Bank5_6_R->SDTR[1] = 0x01010351;
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/* SDRAM initialization sequence */
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/* Clock enable command */
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FMC_Bank5_6_R->SDCMR = 0x00000009;
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tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
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while ((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
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}
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/* Delay */
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for (index=0; index<1000; index++);
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/* PALL command */
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FMC_Bank5_6_R->SDCMR = 0x0000000A;
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timeout = 0xFFFF;
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while ((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
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}
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FMC_Bank5_6_R->SDCMR = 0x000000EB;
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timeout = 0xFFFF;
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while ((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
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}
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FMC_Bank5_6_R->SDCMR = 0x0004400C;
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timeout = 0xFFFF;
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while ((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
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}
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/* Set refresh count */
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tmpreg = FMC_Bank5_6_R->SDRTR;
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FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603 << 1));
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/* Disable write protection */
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tmpreg = FMC_Bank5_6_R->SDCR[1];
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FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
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/* Configure FMC Bank Mapping */
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FMC_Bank1_R->BTCR[0] |= FMC_BMAP_Value;
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/* FMC controller Enable */
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FMC_Bank1_R->BTCR[0] |= 0x80000000;
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/********** SDRAM only *************************************************************************/
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#elif defined (DATA_IN_ExtSDRAM)
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register uint32_t tmpreg = 0, timeout = 0xFFFF;
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register __IO uint32_t index;
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/*-- I/O Ports Configuration ------------------------------------------------------*/
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/* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
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RCC->AHB4ENR |= 0x000001F8;
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/* Connect PDx pins to FMC Alternate function */
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GPIOD->AFR[0] = 0x000000CC;
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GPIOD->AFR[1] = 0xCC000CCC;
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/* Configure PDx pins in Alternate function mode */
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GPIOD->MODER = 0xAFEAFFFA;
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/* Configure PDx pins speed to 100 MHz */
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GPIOD->OSPEEDR = 0xF03F000F;
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/* Configure PDx pins Output type to push-pull */
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GPIOD->OTYPER = 0x00000000;
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/* Configure PDx pins in Pull-up */
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GPIOD->PUPDR = 0x50150005;
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/* Connect PEx pins to FMC Alternate function */
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GPIOE->AFR[0] = 0xC00000CC;
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GPIOE->AFR[1] = 0xCCCCCCCC;
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/* Configure PEx pins in Alternate function mode */
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GPIOE->MODER = 0xAAAABFFA;
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/* Configure PEx pins speed to 100 MHz */
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GPIOE->OSPEEDR = 0xFFFFC00F;
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/* Configure PEx pins Output type to push-pull */
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GPIOE->OTYPER = 0x00000000;
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/* Configure PEx pins in Pull-up */
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GPIOE->PUPDR = 0x55554005;
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/* Connect PFx pins to FMC Alternate function */
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GPIOF->AFR[0] = 0x00CCCCCC;
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GPIOF->AFR[1] = 0xCCCCC000;
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/* Configure PFx pins in Alternate function mode */
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GPIOF->MODER = 0xAABFFAAA;
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/* Configure PFx pins speed to 100 MHz */
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GPIOF->OSPEEDR = 0xFFC00FFF;
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/* Configure PFx pins Output type to push-pull */
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GPIOF->OTYPER = 0x00000000;
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/* Configure PFx pins in Pull-up */
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GPIOF->PUPDR = 0x55400555;
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/* Connect PGx pins to FMC Alternate function */
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GPIOG->AFR[0] = 0x00CCCCCC;
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GPIOG->AFR[1] = 0xC000000C;
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/* Configure PGx pins in Alternate function mode */
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GPIOG->MODER = 0xBFFEFAAA;
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/* Configure PGx pins speed to 100 MHz */
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GPIOG->OSPEEDR = 0xC0030FFF;
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/* Configure PGx pins Output type to push-pull */
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GPIOG->OTYPER = 0x00000000;
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/* Configure PGx pins in Pull-up */
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GPIOG->PUPDR = 0x40010555;
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/* Connect PHx pins to FMC Alternate function */
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GPIOH->AFR[0] = 0xCCC00000;
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GPIOH->AFR[1] = 0xCCCCCCCC;
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/* Configure PHx pins in Alternate function mode */
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GPIOH->MODER = 0xAAAAABFF;
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/* Configure PHx pins speed to 100 MHz */
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GPIOH->OSPEEDR = 0xFFFFFC00;
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/* Configure PHx pins Output type to push-pull */
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GPIOH->OTYPER = 0x00000000;
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/* Configure PHx pins in Pull-up */
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GPIOH->PUPDR = 0x55555400;
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/* Connect PIx pins to FMC Alternate function */
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GPIOI->AFR[0] = 0xCCCCCCCC;
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GPIOI->AFR[1] = 0x00000CC0;
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/* Configure PIx pins in Alternate function mode */
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GPIOI->MODER = 0xFFEBAAAA;
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/* Configure PIx pins speed to 100 MHz */
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GPIOI->OSPEEDR = 0x003CFFFF;
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/* Configure PIx pins Output type to push-pull */
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GPIOI->OTYPER = 0x00000000;
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/* Configure PIx pins in Pull-up */
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GPIOI->PUPDR = 0x00145555;
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/*-- FMC Configuration ------------------------------------------------------*/
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/* Enable the FMC interface clock */
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(RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
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||||||
/* SDRAM Timing and access interface configuration */
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||||||
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/*LoadToActiveDelay = 2
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ExitSelfRefreshDelay = 6
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||||||
SelfRefreshTime = 4
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||||||
RowCycleDelay = 6
|
|
||||||
WriteRecoveryTime = 2
|
|
||||||
RPDelay = 2
|
|
||||||
RCDDelay = 2
|
|
||||||
SDBank = FMC_SDRAM_BANK2
|
|
||||||
ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9
|
|
||||||
RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12
|
|
||||||
MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32
|
|
||||||
InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4
|
|
||||||
CASLatency = FMC_SDRAM_CAS_LATENCY_2
|
|
||||||
WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE
|
|
||||||
SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2
|
|
||||||
ReadBurst = FMC_SDRAM_RBURST_ENABLE
|
|
||||||
ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/
|
|
||||||
|
|
||||||
FMC_Bank5_6_R->SDCR[0] = 0x00001800;
|
|
||||||
FMC_Bank5_6_R->SDCR[1] = 0x00000165;
|
|
||||||
FMC_Bank5_6_R->SDTR[0] = 0x00105000;
|
|
||||||
FMC_Bank5_6_R->SDTR[1] = 0x01010351;
|
|
||||||
|
|
||||||
/* SDRAM initialization sequence */
|
|
||||||
/* Clock enable command */
|
|
||||||
FMC_Bank5_6_R->SDCMR = 0x00000009;
|
|
||||||
tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
|
|
||||||
while ((tmpreg != 0) && (timeout-- > 0))
|
|
||||||
{
|
|
||||||
tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Delay */
|
|
||||||
for (index=0; index<1000; index++);
|
|
||||||
|
|
||||||
/* PALL command */
|
|
||||||
FMC_Bank5_6_R->SDCMR = 0x0000000A;
|
|
||||||
timeout = 0xFFFF;
|
|
||||||
while ((tmpreg != 0) && (timeout-- > 0))
|
|
||||||
{
|
|
||||||
tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
|
|
||||||
}
|
|
||||||
|
|
||||||
FMC_Bank5_6_R->SDCMR = 0x000000EB;
|
|
||||||
timeout = 0xFFFF;
|
|
||||||
while ((tmpreg != 0) && (timeout-- > 0))
|
|
||||||
{
|
|
||||||
tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
|
|
||||||
}
|
|
||||||
|
|
||||||
FMC_Bank5_6_R->SDCMR = 0x0004400C;
|
|
||||||
timeout = 0xFFFF;
|
|
||||||
while ((tmpreg != 0) && (timeout-- > 0))
|
|
||||||
{
|
|
||||||
tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
|
|
||||||
}
|
|
||||||
/* Set refresh count */
|
|
||||||
tmpreg = FMC_Bank5_6_R->SDRTR;
|
|
||||||
FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1));
|
|
||||||
|
|
||||||
/* Disable write protection */
|
|
||||||
tmpreg = FMC_Bank5_6_R->SDCR[1];
|
|
||||||
FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
|
|
||||||
|
|
||||||
/* FMC controller Enable */
|
|
||||||
FMC_Bank1_R->BTCR[0] |= 0x80000000;
|
|
||||||
|
|
||||||
/********** SRAM only **************************************************************************/
|
|
||||||
|
|
||||||
#elif defined(DATA_IN_ExtSRAM)
|
|
||||||
|
|
||||||
/*-- I/O Ports Configuration -----------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
|
||||||
RCC->AHB4ENR |= 0x00000078;
|
|
||||||
|
|
||||||
/* Connect PDx pins to FMC Alternate function */
|
|
||||||
GPIOD->AFR[0] = 0x00CC00CC;
|
|
||||||
GPIOD->AFR[1] = 0xCCCCCCCC;
|
|
||||||
/* Configure PDx pins in Alternate function mode */
|
|
||||||
GPIOD->MODER = 0xAAAAFABA;
|
|
||||||
/* Configure PDx pins speed to 100 MHz */
|
|
||||||
GPIOD->OSPEEDR = 0xFFFF0F0F;
|
|
||||||
/* Configure PDx pins Output type to push-pull */
|
|
||||||
GPIOD->OTYPER = 0x00000000;
|
|
||||||
/* Configure PDx pins in Pull-up */
|
|
||||||
GPIOD->PUPDR = 0x55550505;
|
|
||||||
|
|
||||||
/* Connect PEx pins to FMC Alternate function */
|
|
||||||
GPIOE->AFR[0] = 0xC00CC0CC;
|
|
||||||
GPIOE->AFR[1] = 0xCCCCCCCC;
|
|
||||||
/* Configure PEx pins in Alternate function mode */
|
|
||||||
GPIOE->MODER = 0xAAAABEBA;
|
|
||||||
/* Configure PEx pins speed to 100 MHz */
|
|
||||||
GPIOE->OSPEEDR = 0xFFFFC3CF;
|
|
||||||
/* Configure PEx pins Output type to push-pull */
|
|
||||||
GPIOE->OTYPER = 0x00000000;
|
|
||||||
/* Configure PEx pins in Pull-up */
|
|
||||||
GPIOE->PUPDR = 0x55554145;
|
|
||||||
|
|
||||||
/* Connect PFx pins to FMC Alternate function */
|
|
||||||
GPIOF->AFR[0] = 0x00CCCCCC;
|
|
||||||
GPIOF->AFR[1] = 0xCCCC0000;
|
|
||||||
/* Configure PFx pins in Alternate function mode */
|
|
||||||
GPIOF->MODER = 0xAAFFFAAA;
|
|
||||||
/* Configure PFx pins speed to 100 MHz */
|
|
||||||
GPIOF->OSPEEDR = 0xFF000FFF;
|
|
||||||
/* Configure PFx pins Output type to push-pull */
|
|
||||||
GPIOF->OTYPER = 0x00000000;
|
|
||||||
/* Configure PFx pins in Pull-up */
|
|
||||||
GPIOF->PUPDR = 0x55000555;
|
|
||||||
|
|
||||||
/* Connect PGx pins to FMC Alternate function */
|
|
||||||
GPIOG->AFR[0] = 0x00CCCCCC;
|
|
||||||
GPIOG->AFR[1] = 0x00000C00;
|
|
||||||
/* Configure PGx pins in Alternate function mode */
|
|
||||||
GPIOG->MODER = 0xFFEFFAAA;
|
|
||||||
/* Configure PGx pins speed to 100 MHz */
|
|
||||||
GPIOG->OSPEEDR = 0x00300FFF;
|
|
||||||
/* Configure PGx pins Output type to push-pull */
|
|
||||||
GPIOG->OTYPER = 0x00000000;
|
|
||||||
/* Configure PGx pins in Pull-up */
|
|
||||||
GPIOG->PUPDR = 0x00100555;
|
|
||||||
|
|
||||||
/*-- FMC/FSMC Configuration --------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Enable the FMC/FSMC interface clock */
|
|
||||||
(RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
|
|
||||||
|
|
||||||
/* Configure and enable Bank1_SRAM2 */
|
|
||||||
FMC_Bank1_R->BTCR[4] = 0x00001091;
|
|
||||||
FMC_Bank1_R->BTCR[5] = 0x00110212;
|
|
||||||
FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
|
|
||||||
|
|
||||||
/* FMC controller Enable */
|
|
||||||
FMC_Bank1_R->BTCR[0] |= 0x80000000;
|
|
||||||
|
|
||||||
#endif /* DATA_IN_ExtSRAM */
|
|
||||||
|
|
||||||
(void)(tmp);
|
|
||||||
|
|
||||||
}
|
|
||||||
@@ -51,7 +51,6 @@ void bsp_start_hook_0(void)
|
|||||||
stm32h7_init_peripheral_clocks();
|
stm32h7_init_peripheral_clocks();
|
||||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1);
|
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1);
|
||||||
HAL_Init();
|
HAL_Init();
|
||||||
SystemInit_ExtMemCtl();
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#if __CORTEX_M == 0x07U
|
#if __CORTEX_M == 0x07U
|
||||||
|
|||||||
@@ -19,6 +19,5 @@ source:
|
|||||||
- bsps/arm/stm32h7/boards/stm/nucleo-h743zi/stm32h7-config-osc.c
|
- bsps/arm/stm32h7/boards/stm/nucleo-h743zi/stm32h7-config-osc.c
|
||||||
- bsps/arm/stm32h7/boards/stm/nucleo-h743zi/stm32h7-config-per.c
|
- bsps/arm/stm32h7/boards/stm/nucleo-h743zi/stm32h7-config-per.c
|
||||||
- bsps/arm/stm32h7/boards/stm/nucleo-h743zi/system_stm32h7xx.c
|
- bsps/arm/stm32h7/boards/stm/nucleo-h743zi/system_stm32h7xx.c
|
||||||
- bsps/arm/stm32h7/boards/stm/nucleo-h743zi/ext-mem-ctl.c
|
|
||||||
- bsps/arm/shared/cache/cache-v7m.c
|
- bsps/arm/shared/cache/cache-v7m.c
|
||||||
type: build
|
type: build
|
||||||
|
|||||||
Reference in New Issue
Block a user