sparc: Add LEON3_ASR17_PROCESSOR_INDEX_SHIFT

Add _LEON3_Get_current_processor().

c/src/lib/libbsp/sparc/leon3/include/leon.h

@@ -123,7 +123,7 @@ extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs;  /* LEON3 Interrupt Contr
 extern volatile struct gptimer_regs *LEON3_Timer_Regs; /* LEON3 GP Timer */
 
 /* LEON3 CPU Index of boot CPU */
-extern int LEON3_Cpu_Index;
+extern uint32_t LEON3_Cpu_Index;
 
 /* The external IRQ number, -1 if not external interrupts */
 extern int LEON3_IrqCtrl_EIrq;

c/src/lib/libbsp/sparc/leon3/smp/getcpuid.c

@@ -17,9 +17,6 @@
 
 uint32_t _CPU_SMP_Get_current_processor( void )
 {
-  uint32_t id;
-  __asm__ __volatile__( "rd     %%asr17,%0\n\t" : "=r" (id) : );
-
-  return ((id >> 28) & 0xff);
+  return _LEON3_Get_current_processor();
 }
 

c/src/lib/libbsp/sparc/leon3/startup/bspstart.c

@@ -27,7 +27,7 @@
 int CPU_SPARC_HAS_SNOOPING;
 
 /* Index of CPU, in an AMP system CPU-index may be non-zero */
-int LEON3_Cpu_Index = 0;
+uint32_t LEON3_Cpu_Index = 0;
 
 extern void amba_initialize(void);
 
@@ -50,14 +50,6 @@ static inline int set_snooping(void)
   return (tmp >> 23) & 1;
 }
 
-/* ASM-function used to get the CPU-Index on calling LEON3 CPUs */
-static inline unsigned int get_asr17(void)
-{
-  unsigned int reg;
-  __asm__ (" mov %%asr17, %0 " : "=r"(reg) :);
-  return reg;
-}
-
 /*
  *  bsp_start
  *
@@ -72,7 +64,7 @@ void bsp_start( void )
    * and RTEMS on this CPU, and AMP system with mixed operating
    * systems
    */
-  LEON3_Cpu_Index = (get_asr17() >> 28) & 3;
+  LEON3_Cpu_Index = _LEON3_Get_current_processor();
 
   /* Scan AMBA Plug&Play and parse it into a RAM description (ambapp_plb),
    * find GPTIMER for bus frequency, find IRQ Controller and initialize

c/src/lib/libbsp/sparc/shared/irq_asm.S

@@ -31,7 +31,7 @@
 #if BSP_LEON3_SMP
         /* LEON3 SMP support */
         rd       %asr17, \TMP
-        srl      \TMP, 28, \TMP /* CPU number is upper 4 bits so shift */
+        srl      \TMP, LEON3_ASR17_PROCESSOR_INDEX_SHIFT, \TMP
 #else
         mov      0, \TMP
 #endif

c/src/lib/libbsp/sparc/shared/start/start.S

@@ -224,7 +224,7 @@ SYM(hard_reset):
 
 #if defined(START_LEON3_ENABLE_SMP)
 	rd	%asr17, %o0		! get CPU identifier
-	srl	%o0, 28, %o0		! CPU index is upper 4 bits so shift
+	srl	%o0, LEON3_ASR17_PROCESSOR_INDEX_SHIFT, %o0
 
 	cmp	%o0, 0
 	beq	cpu0

cpukit/score/cpu/sparc/rtems/score/sparc.h

@@ -147,6 +147,8 @@ extern "C" {
 /** This constant is the starting bit position of the IMPL in the PSR. */
 #define SPARC_PSR_IMPL_BIT_POSITION 28   /* bits 28 - 31 */
 
+#define LEON3_ASR17_PROCESSOR_INDEX_SHIFT 28
+
 #ifndef ASM
 
 /**
@@ -292,6 +294,18 @@ void sparc_enable_interrupts(uint32_t psr);
       (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
   } while ( 0 )
 
+static inline uint32_t _LEON3_Get_current_processor( void )
+{
+  uint32_t asr17;
+
+  __asm__ (
+    "rd %%asr17, %0"
+    : "=&r" (asr17)
+  );
+
+  return asr17 >> LEON3_ASR17_PROCESSOR_INDEX_SHIFT;
+}
+
 #endif
 
 #ifdef __cplusplus