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sparc: Add LEON3_ASR17_PROCESSOR_INDEX_SHIFT

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Add _LEON3_Get_current_processor().
This commit is contained in:
Sebastian Huber
2014-02-13 13:00:00 +01:00
parent 945853b7cf
commit ad563618ca
6 changed files with 20 additions and 17 deletions
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2
c/src/lib/libbsp/sparc/leon3/include/leon.h
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@@ -123,7 +123,7 @@ extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; /* LEON3 Interrupt Contr
extern volatile struct gptimer_regs *LEON3_Timer_Regs; /* LEON3 GP Timer */ extern volatile struct gptimer_regs *LEON3_Timer_Regs; /* LEON3 GP Timer */
/* LEON3 CPU Index of boot CPU */ /* LEON3 CPU Index of boot CPU */
extern int LEON3_Cpu_Index; extern uint32_t LEON3_Cpu_Index;
/* The external IRQ number, -1 if not external interrupts */ /* The external IRQ number, -1 if not external interrupts */
extern int LEON3_IrqCtrl_EIrq; extern int LEON3_IrqCtrl_EIrq;

5
c/src/lib/libbsp/sparc/leon3/smp/getcpuid.c
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@@ -17,9 +17,6 @@
uint32_t _CPU_SMP_Get_current_processor( void ) uint32_t _CPU_SMP_Get_current_processor( void )
{ {
uint32_t id; return _LEON3_Get_current_processor();
__asm__ __volatile__( "rd %%asr17,%0\n\t" : "=r" (id) : );
return ((id >> 28) & 0xff);
} }

12
c/src/lib/libbsp/sparc/leon3/startup/bspstart.c
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@@ -27,7 +27,7 @@
int CPU_SPARC_HAS_SNOOPING; int CPU_SPARC_HAS_SNOOPING;
/* Index of CPU, in an AMP system CPU-index may be non-zero */ /* Index of CPU, in an AMP system CPU-index may be non-zero */
int LEON3_Cpu_Index = 0; uint32_t LEON3_Cpu_Index = 0;
extern void amba_initialize(void); extern void amba_initialize(void);
@@ -50,14 +50,6 @@ static inline int set_snooping(void)
return (tmp >> 23) & 1; return (tmp >> 23) & 1;
} }
/* ASM-function used to get the CPU-Index on calling LEON3 CPUs */
static inline unsigned int get_asr17(void)
{
unsigned int reg;
__asm__ (" mov %%asr17, %0 " : "=r"(reg) :);
return reg;
}
/* /*
* bsp_start * bsp_start
* *
@@ -72,7 +64,7 @@ void bsp_start( void )
* and RTEMS on this CPU, and AMP system with mixed operating * and RTEMS on this CPU, and AMP system with mixed operating
* systems * systems
*/ */
LEON3_Cpu_Index = (get_asr17() >> 28) & 3; LEON3_Cpu_Index = _LEON3_Get_current_processor();
/* Scan AMBA Plug&Play and parse it into a RAM description (ambapp_plb), /* Scan AMBA Plug&Play and parse it into a RAM description (ambapp_plb),
* find GPTIMER for bus frequency, find IRQ Controller and initialize * find GPTIMER for bus frequency, find IRQ Controller and initialize

2
c/src/lib/libbsp/sparc/shared/irq_asm.S
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@@ -31,7 +31,7 @@
#if BSP_LEON3_SMP #if BSP_LEON3_SMP
/* LEON3 SMP support */ /* LEON3 SMP support */
rd %asr17, \TMP rd %asr17, \TMP
srl \TMP, 28, \TMP /* CPU number is upper 4 bits so shift */ srl \TMP, LEON3_ASR17_PROCESSOR_INDEX_SHIFT, \TMP
#else #else
mov 0, \TMP mov 0, \TMP
#endif #endif

2
c/src/lib/libbsp/sparc/shared/start/start.S
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@@ -224,7 +224,7 @@ SYM(hard_reset):
#if defined(START_LEON3_ENABLE_SMP) #if defined(START_LEON3_ENABLE_SMP)
rd %asr17, %o0 ! get CPU identifier rd %asr17, %o0 ! get CPU identifier
srl %o0, 28, %o0 ! CPU index is upper 4 bits so shift srl %o0, LEON3_ASR17_PROCESSOR_INDEX_SHIFT, %o0
cmp %o0, 0 cmp %o0, 0
beq cpu0 beq cpu0

14
cpukit/score/cpu/sparc/rtems/score/sparc.h
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@@ -147,6 +147,8 @@ extern "C" {
/** This constant is the starting bit position of the IMPL in the PSR. */ /** This constant is the starting bit position of the IMPL in the PSR. */
#define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */ #define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */
#define LEON3_ASR17_PROCESSOR_INDEX_SHIFT 28
#ifndef ASM #ifndef ASM
/** /**
@@ -292,6 +294,18 @@ void sparc_enable_interrupts(uint32_t psr);
(_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \ (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
} while ( 0 ) } while ( 0 )
static inline uint32_t _LEON3_Get_current_processor( void )
{
uint32_t asr17;
__asm__ (
"rd %%asr17, %0"
: "=&r" (asr17)
);
return asr17 >> LEON3_ASR17_PROCESSOR_INDEX_SHIFT;
}
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus