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2001-03-13 Joel Sherrill <joel@OARcorp.com>

Browse Source 
* Added mongoose-v, mongoose-v/include, and mongoose-v/vectorisrs
	directories.
	* mongoosev/.cvsignore, mongoosev/Makefile.am, mongoosev/README,
	mongoosev/duart/.cvsignore, mongoosev/duart/Makefile.am,
	mongoosev/duart/README.mguart, mongoosev/duart/mg5uart.c,
	mongoosev/duart/mg5uart.h, mongoosev/duart/mg5uart_reg.c,
	mongoosev/include/.cvsignore, mongoosev/include/Makefile.am,
	mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/.cvsignore,
	mongoosev/vectorisrs/Makefile.am, mongoosev/vectorisrs/vectorisrs.c:
	New files.
	* Makefile.am, configure.in, shared/interrupts/Makefile.am,
	shared/interrupts/maxvectors.c: Added support for mongoosev.
	* tx39/vectorisrs/vectorisrs.c: Corrected warning.
This commit is contained in:
Joel Sherrill
2001-03-14 00:49:17 +00:00
parent 7b79761f02
commit acdb655855
21 changed files with 1614 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
c/src/lib/libcpu/mips/ChangeLog
View File

@@ -1,3 +1,19 @@
2001-03-13 Joel Sherrill <joel@OARcorp.com>
* Added mongoose-v, mongoose-v/include, and mongoose-v/vectorisrs
directories.
* mongoosev/.cvsignore, mongoosev/Makefile.am, mongoosev/README,
mongoosev/duart/.cvsignore, mongoosev/duart/Makefile.am,
mongoosev/duart/README.mguart, mongoosev/duart/mg5uart.c,
mongoosev/duart/mg5uart.h, mongoosev/duart/mg5uart_reg.c,
mongoosev/include/.cvsignore, mongoosev/include/Makefile.am,
mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/.cvsignore,
mongoosev/vectorisrs/Makefile.am, mongoosev/vectorisrs/vectorisrs.c:
New files.
* Makefile.am, configure.in, shared/interrupts/Makefile.am,
shared/interrupts/maxvectors.c: Added support for mongoosev.
* tx39/vectorisrs/vectorisrs.c: Corrected warning.
2001-03-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* shared/cache/Makefile.am, tx39/include/Makefile.am:

4
c/src/lib/libcpu/mips/Makefile.am
View File

@@ -7,6 +7,10 @@ ACLOCAL_AMFLAGS = -I ../../../../../aclocal
SHARED_LIB = shared
if mongoosev
CPU_SUBDIR = mongoosev
endif
if tx39
CPU_SUBDIR = tx39
endif

6
c/src/lib/libcpu/mips/configure.in
View File

@@ -31,10 +31,16 @@ AM_CONDITIONAL(r46xx, test "$RTEMS_CPU_MODEL" = "R4600" \
AM_CONDITIONAL(tx39, test "$RTEMS_CPU_MODEL" = "tx3904")
AM_CONDITIONAL(mongoosev, test "$RTEMS_CPU_MODEL" = "mongoosev")
# Explicitly list all Makefiles here
AC_OUTPUT(
Makefile
clock/Makefile
mongoosev/Makefile
mongoosev/duart/Makefile
mongoosev/include/Makefile
mongoosev/vectorisrs/Makefile
shared/Makefile
shared/cache/Makefile
shared/interrupts/Makefile

13
c/src/lib/libcpu/mips/mongoosev/.cvsignore Normal file
View File

@@ -0,0 +1,13 @@
Makefile
Makefile.in
aclocal.m4
config.cache
config.guess
config.log
config.status
config.sub
configure
depcomp
install-sh
missing
mkinstalldirs

11
c/src/lib/libcpu/mips/mongoosev/Makefile.am Normal file
View File

@@ -0,0 +1,11 @@
##
## $Id$
##
AUTOMAKE_OPTIONS = foreign 1.4
ACLOCAL_AMFLAGS = -I ../../../../../../aclocal
SUBDIRS = include duart vectorisrs
include $(top_srcdir)/../../../../../automake/subdirs.am
include $(top_srcdir)/../../../../../automake/local.am

6
c/src/lib/libcpu/mips/mongoosev/README Normal file
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@@ -0,0 +1,6 @@
#
# $Id$
#
The Synova Mongoose-V is a radiation hardened derivative of the
LSI 33K with on-CPU peripherals.

13
c/src/lib/libcpu/mips/mongoosev/duart/.cvsignore Normal file
View File

@@ -0,0 +1,13 @@
Makefile
Makefile.in
aclocal.m4
config.cache
config.guess
config.log
config.status
config.sub
configure
depcomp
install-sh
missing
mkinstalldirs

41
c/src/lib/libcpu/mips/mongoosev/duart/Makefile.am Normal file
View File

@@ -0,0 +1,41 @@
##
## $Id$
##
AUTOMAKE_OPTIONS = foreign 1.4
PGM = $(ARCH)/mg5uart.rel
C_FILES = mg5uart.c mg5uart_reg.c
mg5uart_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../automake/compile.am
include $(top_srcdir)/../../../../../automake/lib.am
$(PROJECT_INCLUDE)/libchip:
@$(mkinstalldirs) $@
$(PROJECT_INCLUDE)/libchip/%.h: %.h
$(INSTALL_DATA) $< $@
#
# (OPTIONAL) Add local stuff here using +=
#
$(PGM): $(mg5uart_rel_OBJECTS)
$(make-rel)
## include_libchip_HEADERS = mg5uart.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip \
$(PROJECT_INCLUDE)/libchip/mg5uart.h
## $(include_libchip_HEADERS:%=$(PROJECT_INCLUDE)/libchip/%)
all-local: $(ARCH) $(PREINSTALL_FILES) $(mg5uart_rel_OBJECTS) $(PGM)
.PRECIOUS: $(PGM)
EXTRA_DIST = mg5uart.c README.mguart mg5uart.c mg5uart.h mg5uart_reg.c
include $(top_srcdir)/../../../../../automake/local.am

105
c/src/lib/libcpu/mips/mongoosev/duart/README.mguart Normal file
View File

@@ -0,0 +1,105 @@
#
# $Id$
#
Configuration Table Use
=======================
sDeviceName
The name of this device.
deviceType
This field must be SERIAL_MG5UART.
pDeviceFns
The device interface control table. This may be:
+ mg5uart_fns for interrupt driven IO
+ mg5uart_fns_polled for polled IO
deviceProbe
This is the address of the routine which probes to see if the device
is present.
pDeviceFlow
This field is ignored as hardware flow control is not currently supported.
ulMargin
This is currently unused.
ulHysteresis
This is currently unused.
pDeviceParams
This is set to the default settings.
ulCtrlPort1
This field is the address of the command register shared by both ports.
ulCtrlPort2
This field is the address of the port being used.
ulDataPort
This field is set to MG5UART_PORTA or MG5UART_PORTB.
getRegister
setRegister
These do NOT follow standard conventions and are ignored.
The register address routines are hard-coded as this is
an on-CPU part and assumed to provide a 32-bit wide interface.
getData
This is address of the RX buffer register.
setData
This is address of the TX buffer register.
ulClock
baudRate Clock
ulIntVector
This is the interrupt vector number associated with this chip.
Example:
#if (CONSOLE_USE_INTERRUPTS)
#define MG5UART_FUNCTIONS &mg5uart_fns
#else
#define MG5UART_FUNCTIONS &mg5uart_fns_polled
#endif
{
"/dev/com0", /* sDeviceName */
SERIAL_MG5UART, /* deviceType */
MG5UART_FUNCTIONS, /* pDeviceFns */
NULL, /* deviceProbe, assume it is there */
NULL, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *) NULL, /* NULL */ /* pDeviceParams */
MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, /* ulCtrlPort1 */
MONGOOSEV_UART0_BASE, /* ulCtrlPort2 */
MG5UART_UART0, /* ulDataPort */
mg5uart_get_register, /* getRegister */
mg5uart_set_register, /* setRegister */
NULL, /* unused */ /* getData */
NULL, /* unused */ /* setData */
12000000, /* ulClock */
MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR /* ulIntVector -- base for port */
}

787
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c Normal file
View File

@@ -0,0 +1,787 @@
/*
* This file contains the termios TTY driver for the UART found
* on the Synova Mongoose-V.
*
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems.h>
#include <rtems/libio.h>
#include <stdlib.h>
#include <libchip/serial.h>
#include <libchip/mg5uart.h>
#include <libchip/sersupp.h>
#include <libcpu/mongoose-v.h>
extern void set_vector( rtems_isr_entry, rtems_vector_number, int );
/*
* Indices of registers
*/
/*
* Per chip context control
*/
typedef struct _mg5uart_context
{
int mate;
} mg5uart_context;
/*
* Define MG5UART_STATIC to nothing while debugging so the entry points
* will show up in the symbol table.
*/
#define MG5UART_STATIC
/* #define MG5UART_STATIC static */
#define MG5UART_SETREG( _base, _register, _value ) \
MONGOOSEV_WRITE_REGISTER( _base, _register, _value )
#define MG5UART_GETREG( _base, _register ) \
MONGOOSEV_READ_REGISTER( _base, _register )
/*
* Console Device Driver Support Functions
*/
MG5UART_STATIC int mg5uart_baud_rate(
int minor,
int baud,
unsigned int *code
);
MG5UART_STATIC void mg5uart_enable_interrupts(
int minor,
int mask
);
/*
* mg5uart_set_attributes
*
* This function sets the UART channel to reflect the requested termios
* port settings.
*/
MG5UART_STATIC int mg5uart_set_attributes(
int minor,
const struct termios *t
)
{
unsigned32 pMG5UART_port;
unsigned32 pMG5UART;
unsigned int cmd;
unsigned int baudcmd;
unsigned int portshift;
rtems_interrupt_level Irql;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2;
/*
* Set the baud rate
*/
if (mg5uart_baud_rate( minor, t->c_cflag, &baudcmd ) == -1)
return -1;
/*
* Base settings
*/
/*
* Base settings
*/
cmd = MONGOOSEV_UART_CMD_TX_ENABLE | MONGOOSEV_UART_CMD_TX_ENABLE;
/*
* Parity
*/
if (t->c_cflag & PARENB) {
cmd |= MONGOOSEV_UART_CMD_PARITY_ENABLE;
if (t->c_cflag & PARODD)
cmd |= MONGOOSEV_UART_CMD_PARITY_ODD;
else
cmd |= MONGOOSEV_UART_CMD_PARITY_EVEN;
} else {
cmd |= MONGOOSEV_UART_CMD_PARITY_DISABLE;
}
/*
* Character Size
*/
if (t->c_cflag & CSIZE) {
switch (t->c_cflag & CSIZE) {
case CS5:
case CS6:
case CS7:
return -1;
break;
case CS8:
/* Mongoose-V only supports CS8 */
break;
}
} /* else default to CS8 */
/*
* Stop Bits
*/
#if 0
if (t->c_cflag & CSTOPB) {
/* 2 stop bits not supported by Mongoose-V uart */
return -1;
}
#endif
/*
* XXX what about CTS/RTS
*/
/* XXX */
/*
* Now write the registers
*/
if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 )
portshift = MONGOOSEV_UART0_CMD_SHIFT;
else
portshift = MONGOOSEV_UART1_CMD_SHIFT;
rtems_interrupt_disable(Irql);
MG5UART_SETREG( pMG5UART, MG5UART_COMMAND_REGISTER, cmd << portshift );
MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
rtems_interrupt_enable(Irql);
return 0;
}
/*
* mg5uart_initialize_context
*
* This function sets the default values of the per port context structure.
*/
MG5UART_STATIC void mg5uart_initialize_context(
int minor,
mg5uart_context *pmg5uartContext
)
{
int port;
unsigned int pMG5UART;
unsigned int pMG5UART_port;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2;
pmg5uartContext->mate = -1;
for (port=0 ; port<Console_Port_Count ; port++ ) {
if ( Console_Port_Tbl[port].ulCtrlPort1 == pMG5UART &&
Console_Port_Tbl[port].ulCtrlPort2 != pMG5UART_port ) {
pmg5uartContext->mate = port;
break;
}
}
}
/*
* mg5uart_init
*
* This function initializes the DUART to a quiecsent state.
*/
MG5UART_STATIC void mg5uart_init(int minor)
{
unsigned32 pMG5UART_port;
unsigned32 pMG5UART;
mg5uart_context *pmg5uartContext;
pmg5uartContext = (mg5uart_context *) malloc(sizeof(mg5uart_context));
Console_Port_Data[minor].pDeviceContext = (void *)pmg5uartContext;
mg5uart_initialize_context( minor, pmg5uartContext );
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2;
/*
* Reset everything and leave this port disabled.
*/
MG5UART_SETREG( pMG5UART, 0, MONGOOSEV_UART_CMD_RESET_BOTH_PORTS );
/*
* Disable interrupts on RX and TX for this port
*/
mg5uart_enable_interrupts( minor, MG5UART_DISABLE_ALL );
}
/*
* mg5uart_open
*
* This function opens a port for communication.
*
* Default state is 9600 baud, 8 bits, No parity, and 1 stop bit.
*/
MG5UART_STATIC int mg5uart_open(
int major,
int minor,
void *arg
)
{
unsigned32 pMG5UART;
unsigned32 pMG5UART_port;
unsigned int vector;
unsigned int cmd;
unsigned int baudcmd;
unsigned int portshift;
rtems_interrupt_level Irql;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2;
vector = Console_Port_Tbl[minor].ulIntVector;
/* XXX default baud rate could be from configuration table */
(void) mg5uart_baud_rate( minor, B9600, &baudcmd );
/*
* Set the DUART channel to a default useable state
* B9600, 8Nx since there is no stop bit control.
*/
cmd = MONGOOSEV_UART_CMD_TX_ENABLE | MONGOOSEV_UART_CMD_RX_ENABLE;
if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 )
portshift = MONGOOSEV_UART0_CMD_SHIFT;
else
portshift = MONGOOSEV_UART1_CMD_SHIFT;
rtems_interrupt_disable(Irql);
MG5UART_SETREG( pMG5UART, MG5UART_COMMAND_REGISTER, cmd << portshift );
MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
rtems_interrupt_enable(Irql);
return RTEMS_SUCCESSFUL;
}
/*
* mg5uart_close
*
* This function shuts down the requested port.
*/
MG5UART_STATIC int mg5uart_close(
int major,
int minor,
void *arg
)
{
unsigned32 pMG5UART;
unsigned32 pMG5UART_port;
unsigned int cmd;
unsigned int portshift;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2;
/*
* Disable interrupts from this channel and then disable it totally.
*/
/* XXX interrupts */
cmd = MONGOOSEV_UART_CMD_TX_DISABLE | MONGOOSEV_UART_CMD_RX_DISABLE;
if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 )
portshift = MONGOOSEV_UART0_CMD_SHIFT;
else
portshift = MONGOOSEV_UART1_CMD_SHIFT;
MG5UART_SETREG( pMG5UART, MG5UART_COMMAND_REGISTER, cmd << portshift );
return(RTEMS_SUCCESSFUL);
}
/*
* mg5uart_write_polled
*
* This routine polls out the requested character.
*/
MG5UART_STATIC void mg5uart_write_polled(
int minor,
char c
)
{
unsigned32 pMG5UART;
unsigned32 pMG5UART_port;
unsigned32 status;
int shift;
int timeout;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2;
if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
/*
* wait for transmitter holding register to be empty
*/
timeout = 1000;
status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER);
while ( 1 ) {
status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
if ( (status & (MONGOOSEV_UART_TX_READY|MONGOOSEV_UART_TX_EMPTY_0)) ==
(MONGOOSEV_UART_TX_READY|MONGOOSEV_UART_TX_EMPTY_0) )
break;
/*
* Yield while we wait
*/
#if 0
if(_System_state_Is_up(_System_state_Get())) {
rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
}
#endif
if(!--timeout) {
break;
}
}
/*
* transmit character
*/
MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, c);
}
/*
* mg5uart_isr_XXX
*
* This is the single interrupt entry point which parcels interrupts
* out to the handlers for specific sources and makes sure that the
* shared handler gets the right arguments.
*
* NOTE: Yes .. this is ugly but it provides 5 interrupt source
* wrappers which are nearly functionally identical.
*/
#define __ISR(_TYPE, _OFFSET) \
MG5UART_STATIC void mg5uart_process_isr_ ## _TYPE ( \
int minor \
); \
\
MG5UART_STATIC rtems_isr mg5uart_isr_ ## _TYPE ( \
rtems_vector_number vector \
) \
{ \
int minor; \
\
for(minor=0 ; minor<Console_Port_Count ; minor++) { \
if( Console_Port_Tbl[minor].deviceType == SERIAL_MG5UART && \
vector == Console_Port_Tbl[minor].ulIntVector + _OFFSET ) { \
mg5uart_process_isr_ ## _TYPE (minor); \
} \
} \
}
__ISR(rx_frame_error, MG5UART_IRQ_RX_FRAME_ERROR)
__ISR(rx_overrun_error, MG5UART_IRQ_RX_OVERRUN_ERROR)
__ISR(tx_empty, MG5UART_IRQ_TX_EMPTY)
__ISR(tx_ready, MG5UART_IRQ_TX_READY)
__ISR(rx_ready, MG5UART_IRQ_RX_READY)
MG5UART_STATIC void mg5uart_process_isr_rx_frame_error(
int minor
)
{
unsigned32 pMG5UART;
int shift;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
/* now clear the error */
MG5UART_SETREG(
pMG5UART,
MG5UART_STATUS_REGISTER,
MONGOOSEV_UART_RX_FRAME_ERROR << shift
);
}
MG5UART_STATIC void mg5uart_process_isr_rx_overrun_error(
int minor
)
{
unsigned32 pMG5UART;
int shift;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
/* now clear the error */
MG5UART_SETREG(
pMG5UART,
MG5UART_STATUS_REGISTER,
MONGOOSEV_UART_RX_OVERRUN_ERROR << shift
);
}
MG5UART_STATIC void mg5uart_process_tx_isr(
int minor,
unsigned32 source_mask
);
MG5UART_STATIC void mg5uart_process_isr_tx_empty(
int minor
)
{
mg5uart_process_tx_isr( minor, MONGOOSEV_UART_TX_EMPTY );
}
MG5UART_STATIC void mg5uart_process_isr_tx_ready(
int minor
)
{
mg5uart_process_tx_isr( minor, MONGOOSEV_UART_TX_READY );
}
MG5UART_STATIC void mg5uart_process_tx_isr(
int minor,
unsigned32 source_mask
)
{
unsigned32 pMG5UART;
int shift;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
if (!rtems_termios_dequeue_characters(
Console_Port_Data[minor].termios_data, 1))
return;
/*
* There are no more characters to transmit so clear the interrupt
* source and disable TX interrupts.
*/
Console_Port_Data[minor].bActive = FALSE;
if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
/* now clear the interrupt source */
MG5UART_SETREG(
pMG5UART,
MG5UART_STATUS_REGISTER,
source_mask << shift
);
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX);
}
MG5UART_STATIC void mg5uart_process_isr_rx_ready(
int minor
)
{
unsigned32 pMG5UART_port;
unsigned char c;
pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2;
c = (unsigned char) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER);
rtems_termios_enqueue_raw_characters(
Console_Port_Data[minor].termios_data,
&c,
1
);
/* reading the RX buffer automatically resets the error */
}
/*
* mg5uart_initialize_interrupts
*
* This routine initializes the console's receive and transmit
* ring buffers and loads the appropriate vectors to handle the interrupts.
*/
MG5UART_STATIC void mg5uart_initialize_interrupts(int minor)
{
unsigned long v;
mg5uart_init(minor);
Console_Port_Data[minor].bActive = FALSE;
v = Console_Port_Tbl[minor].ulIntVector;
set_vector(mg5uart_isr_rx_frame_error, v + MG5UART_IRQ_RX_FRAME_ERROR, 1);
set_vector(mg5uart_isr_rx_overrun_error, v + MG5UART_IRQ_RX_OVERRUN_ERROR, 1);
set_vector(mg5uart_isr_tx_empty, v + MG5UART_IRQ_TX_EMPTY, 1);
set_vector(mg5uart_isr_tx_ready, v + MG5UART_IRQ_TX_READY, 1);
set_vector(mg5uart_isr_rx_ready, v + MG5UART_IRQ_RX_READY, 1);
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX);
}
/*
* mg5uart_write_support_int
*
* Console Termios output entry point when using interrupt driven output.
*/
MG5UART_STATIC int mg5uart_write_support_int(
int minor,
const char *buf,
int len
)
{
unsigned32 Irql;
unsigned32 pMG5UART_port;
pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2;
/*
* We are using interrupt driven output and termios only sends us
* one character at a time.
*/
if ( !len )
return 0;
/*
* Put the character out and enable interrupts if necessary.
*/
rtems_interrupt_disable(Irql);
if ( Console_Port_Data[minor].bActive == FALSE ) {
Console_Port_Data[minor].bActive = TRUE;
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL);
}
MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf);
rtems_interrupt_enable(Irql);
return 1;
}
/*
* mg5uart_write_support_polled
*
* Console Termios output entry point when using polled output.
*
*/
MG5UART_STATIC int mg5uart_write_support_polled(
int minor,
const char *buf,
int len
)
{
int nwrite = 0;
/*
* poll each byte in the string out of the port.
*/
while (nwrite < len) {
/*
* transmit character
*/
mg5uart_write_polled(minor, *buf++);
nwrite++;
}
/*
* return the number of bytes written.
*/
return nwrite;
}
/*
* mg5uart_inbyte_nonblocking_polled
*
* Console Termios polling input entry point.
*/
MG5UART_STATIC int mg5uart_inbyte_nonblocking_polled(
int minor
)
{
unsigned32 pMG5UART;
unsigned32 pMG5UART_port;
unsigned32 status;
int shift;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2;
if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
if ( status & MONGOOSEV_UART_RX_READY ) {
return (int) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER);
} else {
return -1;
}
}
/*
* mg5uart_baud_rate
*/
MG5UART_STATIC int mg5uart_baud_rate(
int minor,
int baud,
unsigned int *code
)
{
rtems_unsigned32 clock;
rtems_unsigned32 tmp_code;
rtems_unsigned32 baud_requested;
baud_requested = baud & CBAUD;
if (!baud_requested)
baud_requested = B9600; /* default to 9600 baud */
baud_requested = termios_baud_to_number( B9600 );
clock = (rtems_unsigned32) Console_Port_Tbl[minor].ulClock;
if (!clock)
rtems_fatal_error_occurred(RTEMS_INVALID_NUMBER);
/*
* Formula is Code = round(ClockFrequency / Baud - 1).
*
* Since this is integer math, we will divide by twice the baud and
* check the remaining odd bit.
*/
tmp_code = (clock / (baud_requested * 2));
if ( tmp_code & 0x01 )
tmp_code = (tmp_code >> 1) + 1;
else
tmp_code = (tmp_code >> 1);
/*
* From section 12.7, "Keep C>100 for best receiver operation."
* That is 100 cycles which is not a lot of instructions. It is
* reasonable to think that the Mongoose-V could not keep
* up with C < 200.
*/
if ( tmp_code < 100 )
return RTEMS_INVALID_NUMBER;
/*
* upper word is receiver baud and lower word is transmitter baud
*/
*code = (tmp_code << 16) | tmp_code;
return 0;
}
/*
* mg5uart_enable_interrupts
*
* This function enables specific interrupt sources on the DUART.
*/
MG5UART_STATIC void mg5uart_enable_interrupts(
int minor,
int mask
)
{
unsigned32 pMG5UART;
unsigned int shift;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
/*
* Enable interrupts on RX and TX -- not break
*/
if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
MG5UART_SETREG(
pMG5UART,
MG5UART_INTERRUPT_MASK_REGISTER,
mask << shift
);
}
/*
* Flow control is only supported when using interrupts
*/
console_fns mg5uart_fns =
{
libchip_serial_default_probe, /* deviceProbe */
mg5uart_open, /* deviceFirstOpen */
NULL, /* deviceLastClose */
NULL, /* deviceRead */
mg5uart_write_support_int, /* deviceWrite */
mg5uart_initialize_interrupts, /* deviceInitialize */
mg5uart_write_polled, /* deviceWritePolled */
mg5uart_set_attributes, /* deviceSetAttributes */
TRUE /* deviceOutputUsesInterrupts */
};
console_fns mg5uart_fns_polled =
{
libchip_serial_default_probe, /* deviceProbe */
mg5uart_open, /* deviceFirstOpen */
mg5uart_close, /* deviceLastClose */
mg5uart_inbyte_nonblocking_polled, /* deviceRead */
mg5uart_write_support_polled, /* deviceWrite */
mg5uart_init, /* deviceInitialize */
mg5uart_write_polled, /* deviceWritePolled */
mg5uart_set_attributes, /* deviceSetAttributes */
FALSE, /* deviceOutputUsesInterrupts */
};

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/*
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef _MG5UART_H_
#define _MG5UART_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* This is the ASCII for "MG5U" which should be unique enough to
* distinguish this type of serial device from others.
*/
#define SERIAL_MG5UART 0x474D5535
#define MG5UART_UART0 0
#define MG5UART_UART1 1
/*
* These are just used in the interface between this driver and
* the read/write register routines when accessing the first
* control port. They are indices of registers from the bases.
*/
/* shared registers from peripheral base (i.e. from ulCtrlPort1) */
#define MG5UART_COMMAND_REGISTER 0
#define MG5UART_STATUS_REGISTER 1
#define MG5UART_INTERRUPT_CAUSE_REGISTER 2
#define MG5UART_INTERRUPT_MASK_REGISTER 3
/* port specific registers from uart base (i.e. from ulCtrlPort2) */
#define MG5UART_RX_BUFFER 0
#define MG5UART_TX_BUFFER 1
#define MG5UART_BAUD_RATE 2
/*
* Interrupt mask values
*/
#define MG5UART_ENABLE_ALL_EXCEPT_TX MONGOOSEV_UART_ALL_RX_STATUS_BITS
#define MG5UART_ENABLE_ALL (MONGOOSEV_UART_ALL_STATUS_BITS)
#define MG5UART_DISABLE_ALL 0x0000
/*
* Assume vectors are sequential.
*/
#define MG5UART_IRQ_RX_FRAME_ERROR 0
#define MG5UART_IRQ_RX_OVERRUN_ERROR 1
#define MG5UART_IRQ_TX_EMPTY 2
#define MG5UART_IRQ_TX_READY 3
#define MG5UART_IRQ_RX_READY 4
/*
* Driver function table
*/
extern console_fns mg5uart_fns;
extern console_fns mg5uart_fns_polled;
/*
* Default register access routines
*/
unsigned32 mg5uart_get_register( /* registers are on 32-bit boundaries */
unsigned32 ulCtrlPort, /* and accessed as word */
unsigned32 ucRegNum
);
void mg5uart_set_register(
unsigned32 ulCtrlPort,
unsigned32 ucRegNum,
unsigned32 ucData
);
#ifdef __cplusplus
}
#endif
#endif /* _MG5UART_H_ */

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c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c Normal file
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/*
* This file contains a typical set of register access routines which may be
* used with the mg5uart chip if accesses to the chip are as follows:
*
* + registers are accessed as unsigned32's
* + registers are only u32-aligned (no address gaps)
*
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems.h>
#ifndef _MG5UART_MULTIPLIER
#define _MG5UART_MULTIPLIER 1
#define _MG5UART_NAME(_X) _X
#define _MG5UART_TYPE unsigned32
#endif
#define CALCULATE_REGISTER_ADDRESS( _base, _reg ) \
(_MG5UART_TYPE *)((_base) + ((_reg) * _MG5UART_MULTIPLIER ))
/*
* MG5UART Get Register Routine
*/
unsigned8 _MG5UART_NAME(mg5uart_get_register)(
unsigned32 ulCtrlPort,
unsigned8 ucRegNum
)
{
_MG5UART_TYPE *port;
port = CALCULATE_REGISTER_ADDRESS( ulCtrlPort, ucRegNum );
return *port;
}
/*
* MG5UART Set Register Routine
*/
void _MG5UART_NAME(mg5uart_set_register)(
unsigned32 ulCtrlPort,
unsigned8 ucRegNum,
unsigned8 ucData
)
{
_MG5UART_TYPE *port;
port = CALCULATE_REGISTER_ADDRESS( ulCtrlPort, ucRegNum );
*port = ucData;
}

13
c/src/lib/libcpu/mips/mongoosev/include/.cvsignore Normal file
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Makefile
Makefile.in
aclocal.m4
config.cache
config.guess
config.log
config.status
config.sub
configure
depcomp
install-sh
missing
mkinstalldirs

22
c/src/lib/libcpu/mips/mongoosev/include/Makefile.am Normal file
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##
## $Id$
##
AUTOMAKE_OPTIONS = foreign 1.4
H_FILES = mongoose-v.h
$(PROJECT_INCLUDE)/libcpu:
$(mkinstalldirs) $@
$(PROJECT_INCLUDE)/libcpu/%.h: %.h
$(INSTALL_DATA) $< $@
TMPINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu \
$(H_FILES:%.h=$(PROJECT_INCLUDE)/libcpu/%.h)
all-local: $(TMPINSTALL_FILES)
EXTRA_DIST = mongoose-v.h
include $(top_srcdir)/../../../../../automake/local.am

281
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/*
* MIPS Mongoose-V specific information
*
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __MONGOOSEV_h
#define __MONGOOSEV_h
/*
* Macros to assist in accessing memory mapped Mongoose registers
*/
#define MONGOOSEV_READ( _base ) \
*((volatile unsigned32 *)(_base))
#define MONGOOSEV_WRITE( _base, _value ) \
*((volatile unsigned32 *)(_base)) = (_value)
#define MONGOOSEV_READ_REGISTER( _base, _register ) \
*((volatile unsigned32 *)((_base) + (_register)))
#define MONGOOSEV_WRITE_REGISTER( _base, _register, _value ) \
*((volatile unsigned32 *)((_base) + (_register))) = (_value)
/*
* BIU and DRAM Registers
*/
#define MONGOOSEV_BIU_CACHE_CONFIGURATION_REGISTER 0xFFFE0130
#define MONGOOSEV_DRAM_CONFIGURATION_REGISTER 0xFFFE0120
#define MONGOOSEV_REFRESH_TIMER_INITIAL_COUNTER_REGISTER 0xFFFE0010
#define MONGOOSEV_WAIT_STATE_CONFIGURATION_REGISTER_BASE 0xFFFE0100
/*
* Peripheral Function Addresses
*
* NOTE: Status and Interrupt Cause use the same bits
*/
#define MONGOOSEV_PERIPHERAL_COMMAND_REGISTER 0xFFFE0180
#define MONGOOSEV_PERIPHERAL_STATUS_REGISTER 0xFFFE0184
#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER 0xFFFE0188
#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER 0xFFFE018C
/* UART Bits in Peripheral Command Register Bits (TX/RX tied together here) */
#define MONGOOSEV_UART_CMD_RESET_BOTH_PORTS 0x0001
#define MONGOOSEV_UART_CMD_LOOPBACK_CTSN 0x0002
#define MONGOOSEV_UART_CMD_LOOPBACK_RXTX 0x0004
#define MONGOOSEV_UART_CMD_TX_ENABLE 0x001
#define MONGOOSEV_UART_CMD_TX_DISABLE 0x000
#define MONGOOSEV_UART_CMD_RX_ENABLE 0x002
#define MONGOOSEV_UART_CMD_RX_DISABLE 0x000
#define MONGOOSEV_UART_CMD_TX_READY 0x004
#define MONGOOSEV_UART_CMD_PARITY_ENABLE 0x008
#define MONGOOSEV_UART_CMD_PARITY_DISABLE 0x000
#define MONGOOSEV_UART_CMD_PARITY_EVEN 0x800
#define MONGOOSEV_UART_CMD_PARITY_ODD 0x000
#define MONGOOSEV_UART0_CMD_SHIFT 5
#define MONGOOSEV_UART1_CMD_SHIFT 11
#define MONGOOSEV_UART_CMD_TX_ENABLE_0 \
(MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_RX_ENABLE_0 \
(MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_TX_READY_0 \
(MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_ENABLE_0 \
(MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_DISABLE_0 \
(MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_EVEN_0 \
(MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_ODD_0 \
(MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_TX_ENABLE_1 \
(MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_RX_ENABLE_1 \
(MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_TX_READY_1 \
(MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_ENABLE_1 \
(MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_DISABLE_1 \
(MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_EVEN_1 \
(MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_ODD_1 \
(MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT)
/* UART Bits in Peripheral Status and Interrupt Cause Register */
#define MONGOOSEV_UART_RX_FRAME_ERROR 0x0001
#define MONGOOSEV_UART_RX_OVERRUN_ERROR 0x0002
#define MONGOOSEV_UART_TX_EMPTY 0x0004
#define MONGOOSEV_UART_TX_READY 0x0008
#define MONGOOSEV_UART_RX_READY 0x0010
#define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x0003
#define MONGOOSEV_UART_ALL_STATUS_BITS 0x001F
/*
* The Peripheral Interrupt Status, Cause, and Mask registers have the
* same bit assignments although some revisions of the document have
* the Cause and Status registers incorrect.
*/
#define MONGOOSEV_UART0_IRQ_SHIFT 11
#define MONGOOSEV_UART1_IRQ_SHIFT 17
#define MONGOOSEV_UART_FRAME_ERROR_1 \
(MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_RX_OVERRUN_ERROR_1 \
(MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_TX_EMPTY_1 \
(MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_TX_READY_1 \
(MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_RX_READY_1 \
(MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_FRAME_ERROR_0 \
(MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_RX_OVERRUN_ERROR_0 \
(MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_TX_EMPTY_0 \
(MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_TX_READY_0 \
(MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_RX_READY_0 \
(MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
/*
* Bits in the Peripheral Interrupt Mask Register
*/
/*
** Interrupt Status/Cause/Mask register bits - from 31 to 0
*/
#define MONGOOSEV_EDAC_SERR_BIT 0x80000000
#define MONGOOSEV_EDAC_MERR_BIT 0x40000000
/* 29 - 24 reserved */
#define MONGOOSEV_UART_0_RX_READY 0x00008000
#define MONGOOSEV_UART_0_TX_READY 0x00004000
#define MONGOOSEV_UART_0_TX_EMPTY 0x00002000
#define MONGOOSEV_UART_0_RX_OVERRUN 0x00001000
#define MONGOOSEV_UART_0_FRAME_ERROR 0x00000800
#define MONGOOSEV_UART_0_RESERVED 0x00000400
#define MONGOOSEV_UART_1_RX_READY 0x00200000
#define MONGOOSEV_UART_1_TX_READY 0x00100000
#define MONGOOSEV_UART_1_TX_EMPTY 0x00080000
#define MONGOOSEV_UART_1_RX_OVERRUN 0x00040000
#define MONGOOSEV_UART_1_FRAME_ERROR 0x00020000
#define MONGOOSEV_UART_1_RESERVED 0x00010000
#define MONGOOSEV_MAVN_WRITE_ACCESS 0x00400000
#define MONGOOSEV_MAVN_READ_ACCESS 0x00800000
#define MONGOOSEV_EXTERN_INT_9 0x00000200
#define MONGOOSEV_EXTERN_INT_8 0x00000100
#define MONGOOSEV_EXTERN_INT_7 0x00000080
#define MONGOOSEV_EXTERN_INT_6 0x00000040
#define MONGOOSEV_EXTERN_INT_5 0x00000020
#define MONGOOSEV_EXTERN_INT_4 0x00000010
#define MONGOOSEV_EXTERN_INT_3 0x00000008
#define MONGOOSEV_EXTERN_INT_2 0x00000004
#define MONGOOSEV_EXTERN_INT_1 0x00000002
#define MONGOOSEV_EXTERN_INT_0 0x00000001
/*
* EDAC Registers
*/
#define MONGOOSEV_EDAC_ERROR_ADDRESS_REGISTER 0xFFFE0190
#define MONGOOSEV_EDAC_PARITY_TEST_MODE_REGISTER 0xFFFE0194
/*
* MAVN Registers
*/
#define MONGOOSEV_MAVN_TEST_REGISTER 0xFFFE01B4
#define MONGOOSEV_MAVN_ACCESS_PRIVILEGE_REGISTER 0xFFFE01B8
#define MONGOOSEV_MAVN_ACCESS_VIOLATION_REGISTER 0xFFFE01BC
#define MONGOOSEV_MAVN_RANGE_0_REGISTER 0xFFFE01C0
#define MONGOOSEV_MAVN_RANGE_1_REGISTER 0xFFFE01C4
#define MONGOOSEV_MAVN_RANGE_2_REGISTER 0xFFFE01C8
#define MONGOOSEV_MAVN_RANGE_3_REGISTER 0xFFFE01CC
#define MONGOOSEV_MAVN_RANGE_4_REGISTER 0xFFFE01D0
#define MONGOOSEV_MAVN_RANGE_5_REGISTER 0xFFFE01D4
#define MONGOOSEV_MAVN_RANGE_6_REGISTER 0xFFFE01D8
#define MONGOOSEV_MAVN_RANGE_7_REGISTER 0xFFFE01DC
/*
* Timer Base Addresses, Offsets, and Values
*/
#define MONGOOSEV_TIMER1_BASE 0xFFFE0000
#define MONGOOSEV_TIMER2_BASE 0xFFFE0008
#define MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER 0
#define MONGOOSEV_TIMER_CONTROL_REGISTER 4
/* Timer Control Register Constants */
#define MONGOOSEV_TIMER_CONTROL_COUNTER_ENABLE 0x04
#define MONGOOSEV_TIMER_CONTROL_INTERRUPT_ENABLE 0x02
#define MONGOOSEV_TIMER_CONTROL_TIMEOUT 0x01
/*
* UART Base Addresses and Offsets
*
* Many bits in the peripheral command register are UART related
* and the bits are defined there.
*/
#define MONGOOSEV_UART0_BASE 0xFFFE01E8
#define MONGOOSEV_UART1_BASE 0xFFFE01F4
#define MONGOOSEV_RX_BUFFER 0
#define MONGOOSEV_TX_BUFFER 4
#define MONGOOSEV_BAUD_RATE 8
/*
* Interrupt Vector Numbers
*
* NOTE: IRQ INT5 is logical or of peripheral cause register
* per p. 5-22 of Mongoose-V manual.
*/
#define MONGOOSEV_IRQ_INT0 0
#define MONGOOSEV_IRQ_TIMER1 MONGOOSEV_IRQ_INT0
#define MONGOOSEV_IRQ_INT1 1
#define MONGOOSEV_IRQ_TIMER2 MONGOOSEV_IRQ_INT1
#define MONGOOSEV_IRQ_INT2 2
#define MONGOOSEV_IRQ_INT4 3
/* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */
#define MONGOOSEV_IRQ_PERIPHERAL_BASE 4
#define MONGOOSEV_IRQ_XINT0 4
#define MONGOOSEV_IRQ_XINT1 5
#define MONGOOSEV_IRQ_XINT2 6
#define MONGOOSEV_IRQ_XINT3 7
#define MONGOOSEV_IRQ_XINT4 8
#define MONGOOSEV_IRQ_XINT5 9
#define MONGOOSEV_IRQ_XINT6 10
#define MONGOOSEV_IRQ_XINT7 11
#define MONGOOSEV_IRQ_XINT8 12
#define MONGOOSEV_IRQ_XINT9 13
#define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION 14
#define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION 15
#define MONGOOSEV_IRQ_RESERVED_BIT_12 16
#define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR 17
#define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR 18
#define MONGOOSEV_IRQ_UART1_TX_EMPTY 19
#define MONGOOSEV_IRQ_UART1_TX_READY 20
#define MONGOOSEV_IRQ_UART1_RX_READY 21
#define MONGOOSEV_IRQ_RESERVED_BIT_18 22
#define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR 23
#define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR 24
#define MONGOOSEV_IRQ_UART0_TX_EMPTY 25
#define MONGOOSEV_IRQ_UART0_TX_READY 26
#define MONGOOSEV_IRQ_UART0_RX_READY 27
#define MONGOOSEV_IRQ_RESERVED_24 28
#define MONGOOSEV_IRQ_RESERVED_25 29
#define MONGOOSEV_IRQ_RESERVED_26 30
#define MONGOOSEV_IRQ_RESERVED_27 31
#define MONGOOSEV_IRQ_RESERVED_28 32
#define MONGOOSEV_IRQ_RESERVED_29 33
#define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR 34
#define MONGOOSEV_IRQ_CORRECTABLE_ERROR 35
#define MONGOOSEV_IRQ_SOFTWARE_1 36
#define MONGOOSEV_IRQ_SOFTWARE_2 37
#endif

13
c/src/lib/libcpu/mips/mongoosev/vectorisrs/.cvsignore Normal file
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Makefile
Makefile.in
aclocal.m4
config.cache
config.guess
config.log
config.status
config.sub
configure
depcomp
install-sh
missing
mkinstalldirs

30
c/src/lib/libcpu/mips/mongoosev/vectorisrs/Makefile.am Normal file
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##
## $Id$
##
AUTOMAKE_OPTIONS = foreign 1.4
PGM = $(ARCH)/vectorisrs.rel
C_FILES = vectorisrs.c
vectorisrs_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../automake/compile.am
include $(top_srcdir)/../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
#
$(PGM): $(vectorisrs_rel_OBJECTS)
$(make-rel)
all-local: $(ARCH) $(vectorisrs_rel_OBJECTS) $(PGM)
.PRECIOUS: $(PGM)
EXTRA_DIST = vectorisrs.c
include $(top_srcdir)/../../../../../automake/local.am

79
c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c Normal file
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/*
* ISR Vectoring support for the Synova Mongoose-V.
*
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems.h>
#include <stdlib.h>
#include <libcpu/mongoose-v.h>
#define mips_get_cause( _cause ) \
do { \
asm volatile( "mfc0 %0, $13; nop" : "=r" (_cause) : ); \
} while (0)
#define CALL_ISR(_vector) \
do { \
if ( _ISR_Vector_table[_vector] ) \
(_ISR_Vector_table[_vector])(_vector); \
else \
mips_default_exception(_vector); \
} while (0)
#include <bspIo.h> /* for printk */
void mips_default_exception( int vector )
{
printk( "Unhandled exception %d\n", vector );
rtems_fatal_error_occurred(1);
}
void mips_vector_isr_handlers( void )
{
unsigned int sr;
unsigned int cause;
int bit;
unsigned int pf_icr;
mips_get_sr( sr );
mips_get_cause( cause );
cause &= (sr & SR_IMASK);
cause >>= CAUSE_IPSHIFT;
if ( cause & 0x04 ) /* IP[0] ==> INT0 == TIMER1 */
CALL_ISR( MONGOOSEV_IRQ_TIMER1 );
if ( cause & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/
CALL_ISR( MONGOOSEV_IRQ_TIMER2 );
if ( cause & 0x10 ) /* IP[2] ==> INT2 */
CALL_ISR( MONGOOSEV_IRQ_INT2 );
if ( cause & 0x20 ) /* IP[3] ==> INT4 */
CALL_ISR( MONGOOSEV_IRQ_INT4 );
if ( cause & 0x40 ) { /* IP[4] ==> INT5 */
pf_icr =
MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER );
/* XXX if !pf_icr */
for ( bit=0 ; bit <= 31 ; bit++, pf_icr >>= 1 ) {
if ( pf_icr & 1 )
CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit );
}
}
if ( cause & 0x02 ) /* SW[0] */
CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1 );
if ( cause & 0x01 ) /* IP[1] */
CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2 );
}

4
c/src/lib/libcpu/mips/shared/interrupts/Makefile.am
View File

@@ -24,6 +24,10 @@ if tx39
EXTRA_FLAGS = -DTX39
endif
if mongoosev
EXTRA_FLAGS = -DMONGOOSEV
endif
AM_CPPFLAGS += $(EXTRA_FLAGS)
$(PGM): $(interrupts_rel_OBJECTS)

21
c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c
View File

@@ -14,14 +14,29 @@
/*
* The tx3904 attaches 4 of the eight interrupt bits to an on-CPU interrupt
* controller so that these four bits map to 16 unique interrupts.
* So you have: 2 software interrupts, an NMI, and 16 others.
* The Toshiba TX3904 attaches 4 of the eight interrupt bits to an
* on-CPU interrupt controller so that these four bits map to 16
* unique interrupts. So you have: 2 software interrupts, an NMI,
* and 16 others.
*/
#if defined(TX39)
#define MAX_VECTORS 19
#endif
/*
* The Synova Mongoose-V attached one of the eight interrupt bits
* to a Peripheral Function Interrupt Cause Register on-CPU.
* This results in: 2 software interrupts, 5 interrupts
* through the IP bits, and 32 more from the PFICR. Some of
* these are reserved but for simplicity in processing, we
* reserve slots for those bits anyway.
*/
#if defined(MONGOOSEV)
#define MAX_VECTORS 37
#endif
#ifndef MAX_VECTORS
#define MAX_VECTORS 8
#endif

2
c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
View File

@@ -19,6 +19,8 @@
mips_default_exception(_vector); \
} while (0)
#include <bspIo.h> /* for printk */
void mips_default_exception( int vector )
{
printk( "Unhandled exception %d\n", vector );