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bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.

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Pavel Pisa
2016-07-03 09:30:20 +02:00
parent 0e507d5510
commit abea02a832
1 changed files with 4 additions and 0 deletions
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4
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
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@@ -72,6 +72,10 @@ extern "C" {
/* These two defines also ensure that the rtems_cache_* functions have bodies */
#define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT
#define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
#if defined(__ARM_ARCH_7A__)
/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */
#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
#endif
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS