Added DMV177 times files and made this all regenerate with two timing

chapters.

doc/supplements/powerpc/Makefile

@@ -23,7 +23,8 @@ COMMON_FILES=../../common/cpright.texi ../../common/setup.texi \
 
 FILES= $(PROJECT).texi \
   bsp.texi callconv.texi cpumodel.texi cputable.texi fatalerr.texi \
-  intr.texi memmodel.texi preface.texi timetbl.texi timedata.texi wksheets.texi 
+  intr.texi memmodel.texi preface.texi timetbl.texi timedata.texi \
+  timedatadmv177.texi timetbldmv177.texi wksheets.texi 
 
 INFOFILES=$(wildcard $(PROJECT) $(PROJECT)-*)
 
@@ -50,9 +51,13 @@ intr.texi: intr.t PSIM_TIMES
 	mv intr.t.fixed intr.texi
 
 timetbl.t: ../../common/timetbl.t
-	sed -e 's/TIMETABLE_NEXT_LINK/Command and Variable Index/' \
+	sed -e 's/TIMETABLE_NEXT_LINK/DMV177 Timing Data/' \
             <../../common/timetbl.t >timetbl.t
 
+timetbldmv177.t: ../../common/timetbl.t
+	sed -e 's/TIMETABLE_NEXT_LINK/Command and Variable Index/' \
+            <../../common/timetbl.t >timetbldmv177.t
+
 timetbl.texi: timetbl.t PSIM_TIMES
 	${REPLACE} -p PSIM_TIMES timetbl.t
 	mv timetbl.t.fixed timetbl.texi
@@ -61,9 +66,17 @@ timedata.texi: timedata.t PSIM_TIMES
 	${REPLACE} -p PSIM_TIMES timedata.t
 	mv timedata.t.fixed timedata.texi
 
+timetbldmv177.texi: timetbldmv177.t DMV177_TIMES
+	${REPLACE} -p DMV177_TIMES timetbldmv177.t
+	mv timetbldmv177.t.fixed timetbldmv177.texi
+
+timedatadmv177.texi: timedatadmv177.t DMV177_TIMES
+	${REPLACE} -p DMV177_TIMES timedatadmv177.t
+	mv timedatadmv177.t.fixed timedatadmv177.texi
+
 wksheets.t: ../../common/wksheets.t
 	sed -e 's/WORKSHEETS_PREVIOUS_LINK/Processor Dependent Information Table CPU Dependent Information Table/' \
-            -e 's/WORKSHEETS_NEXT_LINK/PPC603e Timing Data/' \
+            -e 's/WORKSHEETS_NEXT_LINK/PSIM Timing Data/' \
             <../../common/wksheets.t >wksheets.t
 
 wksheets.texi: wksheets.t PSIM_TIMES
@@ -81,6 +94,7 @@ clean:
 	rm -f $(PROJECT) $(PROJECT)-*
 	rm -f c_$(PROJECT) c_$(PROJECT)-*
 	rm -f timedata.texi timetbl.texi intr.texi wksheets.texi
+	rm -f timedatadmv177.texi timetbldmv177.texi
 	rm -f timetbl.t wksheets.t
 	rm -f *.fixed _*
 

doc/supplements/powerpc/PSIM_TIMES

@@ -7,6 +7,7 @@
 #
 #  CPU Model Information
 #
+RTEMS_BSP       PSIM
 RTEMS_CPU_MODEL PPC603e
 #
 #  Interrupt Latency

doc/supplements/powerpc/memmodel.t

@@ -46,8 +46,8 @@ in the Block Address Translation (BAT) to convert these addresses.
 Implementations of the PowerPC architecture may be thirty-two or sixty-four bit.
 The PowerPC architecture supports a flat thirty-two or sixty-four bit address
 space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
-gigabytes) in thirty-two bit implementations or 0xFFFFFFFFFFFFFFFF 
-(XXX) in sixty-four bit implementations.  Each address is represented
+gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF 
+in sixty-four bit implementations.  Each address is represented
 by either a thirty-two bit or sixty-four bit value and is byte addressable.  
 The address may be used to reference a single byte, half-word
 (2-bytes), word (4 bytes), or in sixty-four bit implementations a

doc/supplements/powerpc/memmodel.texi

@@ -46,8 +46,8 @@ in the Block Address Translation (BAT) to convert these addresses.
 Implementations of the PowerPC architecture may be thirty-two or sixty-four bit.
 The PowerPC architecture supports a flat thirty-two or sixty-four bit address
 space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
-gigabytes) in thirty-two bit implementations or 0xFFFFFFFFFFFFFFFF 
-(XXX) in sixty-four bit implementations.  Each address is represented
+gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF 
+in sixty-four bit implementations.  Each address is represented
 by either a thirty-two bit or sixty-four bit value and is byte addressable.  
 The address may be used to reference a single byte, half-word
 (2-bytes), word (4 bytes), or in sixty-four bit implementations a

doc/supplements/powerpc/powerpc.texi

@@ -73,6 +73,7 @@ END-INFO-DIR-ENTRY
 @include wksheets.texi
 @include ../../common/timing.texi
 @include timedata.texi
+@include timedatadmv177.texi
 @ifinfo
 @node Top, Preface, (dir), (dir)
 @top c_powerpc
@@ -90,7 +91,8 @@ This is the online version of the RTEMS PowerPC Applications Supplement.
 * Processor Dependent Information Table::
 * Memory Requirements::
 * Timing Specification::
-* PPC603e Timing Data::
+* PSIM Timing Data::
+* DMV177 Timing Data::
 * Command and Variable Index::
 * Concept Index::
 @end menu
@@ -101,7 +103,7 @@ This is the online version of the RTEMS PowerPC Applications Supplement.
 @c Need to copy the emacs stuff and "trailer stuff" (index, toc) into here
 @c
 
-@node Command and Variable Index, Concept Index, PPC603e Timing Data Rate Monotonic Manager, Top
+@node Command and Variable Index, Concept Index, DMV177 Timing Data Rate Monotonic Manager, Top
 @unnumbered Command and Variable Index
 
 There are currently no Command and Variable Index entries.

doc/supplements/powerpc/timeDMV177.t

@@ -0,0 +1,139 @@
+@c
+@c  COPYRIGHT (c) 1988-1998.
+@c  On-Line Applications Research Corporation (OAR).
+@c  All rights reserved.
+@c
+@c  $Id$
+@c
+
+@include ../../common/timemac.texi
+@tex
+\global\advance \smallskipamount by -4pt
+@end tex
+
+@ifinfo
+@node DMV177 Timing Data, DMV177 Timing Data Introduction, PSIM Timing Data Rate Monotonic Manager, Top
+@end ifinfo
+@chapter DMV177 Timing Data
+@ifinfo
+@menu
+* DMV177 Timing Data Introduction::
+* DMV177 Timing Data Hardware Platform::
+* DMV177 Timing Data Interrupt Latency::
+* DMV177 Timing Data Context Switch::
+* DMV177 Timing Data Directive Times::
+* DMV177 Timing Data Task Manager::
+* DMV177 Timing Data Interrupt Manager::
+* DMV177 Timing Data Clock Manager::
+* DMV177 Timing Data Timer Manager::
+* DMV177 Timing Data Semaphore Manager::
+* DMV177 Timing Data Message Manager::
+* DMV177 Timing Data Event Manager::
+* DMV177 Timing Data Signal Manager::
+* DMV177 Timing Data Partition Manager::
+* DMV177 Timing Data Region Manager::
+* DMV177 Timing Data Dual-Ported Memory Manager::
+* DMV177 Timing Data I/O Manager::
+* DMV177 Timing Data Rate Monotonic Manager::
+@end menu
+@end ifinfo
+
+@ifinfo
+@node DMV177 Timing Data Introduction, DMV177 Timing Data Hardware Platform, DMV177 Timing Data, DMV177 Timing Data
+@end ifinfo
+@section Introduction
+
+The timing data for RTEMS on the DMV177 implementation
+of the PowerPC architecture is provided along with the target
+dependent aspects concerning the gathering of the timing data.
+The hardware platform used to gather the times is described to
+give the reader a better understanding of each directive time
+provided.  Also, provided is a description of the interrupt
+latency and the context switch times as they pertain to the
+PowerPC version of RTEMS.
+
+@ifinfo
+@node DMV177 Timing Data Hardware Platform, DMV177 Timing Data Interrupt Latency, DMV177 Timing Data Introduction, DMV177 Timing Data
+@end ifinfo
+@section Hardware Platform
+
+All times reported in this chapter were measured using the PowerPC
+Instruction Simulator (PSIM). PSIM simulates a variety of PowerPC
+6xx models with the DMV177 being used as the basis for the measurements
+reported in this chapter.
+
+The PowerPC decrementer register was was used to gather
+all timing information.  In real hardware implementations
+of the PowerPC architecture, this register would typically
+count something like CPU cycles or be a function of the clock
+speed.  However, wth PSIM each count of the decrementer register 
+represents an instruction.  Thus all measurements in this 
+chapter are reported as the actual number of instructions
+executed.  All sources of hardware interrupts were disabled,
+although traps were enabled and the interrupt level of the
+PowerPC allows all interrupts.
+
+@ifinfo
+@node DMV177 Timing Data Interrupt Latency, DMV177 Timing Data Context Switch, DMV177 Timing Data Hardware Platform, DMV177 Timing Data
+@end ifinfo
+@section Interrupt Latency
+
+The maximum period with traps disabled or the
+processor interrupt level set to it's highest value inside RTEMS
+is less than RTEMS_MAXIMUM_DISABLE_PERIOD
+microseconds including the instructions which
+disable and re-enable interrupts.  The time required for the
+PowerPC to vector an interrupt and for the RTEMS entry overhead
+before invoking the user's trap handler are a total of 
+RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
+microseconds.  These combine to yield a worst case interrupt
+latency of less than RTEMS_MAXIMUM_DISABLE_PERIOD +
+RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK microseconds at 
+RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz.
+[NOTE:  The maximum period with interrupts disabled was last
+determined for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
+
+The maximum period with interrupts disabled within
+RTEMS is hand-timed with some assistance from PSIM.  The maximum
+period with interrupts disabled with RTEMS occurs .... XXX
+
+The interrupt vector and entry overhead time was
+generated on the PSIM benchmark platform using the PowerPC's
+decrementer register.  This register was programmed to generate
+an interrupt after one countdown.
+
+@ifinfo
+@node DMV177 Timing Data Context Switch, DMV177 Timing Data Directive Times, DMV177 Timing Data Interrupt Latency, DMV177 Timing Data
+@end ifinfo
+@section Context Switch
+
+The RTEMS processor context switch time is XXX
+microseconds on the PSIM benchmark platform when no floating
+point context is saved or restored.  Additional execution time
+is required when a TASK_SWITCH user extension is configured.
+The use of the TASK_SWITCH extension is application dependent.
+Thus, its execution time is not considered part of the raw
+context switch time.
+
+Since RTEMS was designed specifically for embedded
+missile applications which are floating point intensive, the
+executive is optimized to avoid unnecessarily saving and
+restoring the state of the numeric coprocessor.  The state of
+the numeric coprocessor is only saved when an FLOATING_POINT
+task is dispatched and that task was not the last task to
+utilize the coprocessor.  In a system with only one
+FLOATING_POINT task, the state of the numeric coprocessor will
+never be saved or restored.  When the first FLOATING_POINT task
+is dispatched, RTEMS does not need to save the current state of
+the numeric coprocessor.
+
+The following table summarizes the context switch
+times for the PSIM benchmark platform:
+
+@include timetbldmv177.texi
+
+@tex
+\global\advance \smallskipamount by 4pt
+@end tex
+
+

doc/supplements/powerpc/timePSIM.t

@@ -12,38 +12,38 @@
 @end tex
 
 @ifinfo
-@node PPC603e Timing Data, PPC603e Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
+@node RTEMS_BSP Timing Data, RTEMS_BSP Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
 @end ifinfo
-@chapter PPC603e Timing Data
+@chapter RTEMS_BSP Timing Data
 @ifinfo
 @menu
-* PPC603e Timing Data Introduction::
-* PPC603e Timing Data Hardware Platform::
-* PPC603e Timing Data Interrupt Latency::
-* PPC603e Timing Data Context Switch::
-* PPC603e Timing Data Directive Times::
-* PPC603e Timing Data Task Manager::
-* PPC603e Timing Data Interrupt Manager::
-* PPC603e Timing Data Clock Manager::
-* PPC603e Timing Data Timer Manager::
-* PPC603e Timing Data Semaphore Manager::
-* PPC603e Timing Data Message Manager::
-* PPC603e Timing Data Event Manager::
-* PPC603e Timing Data Signal Manager::
-* PPC603e Timing Data Partition Manager::
-* PPC603e Timing Data Region Manager::
-* PPC603e Timing Data Dual-Ported Memory Manager::
-* PPC603e Timing Data I/O Manager::
-* PPC603e Timing Data Rate Monotonic Manager::
+* RTEMS_BSP Timing Data Introduction::
+* RTEMS_BSP Timing Data Hardware Platform::
+* RTEMS_BSP Timing Data Interrupt Latency::
+* RTEMS_BSP Timing Data Context Switch::
+* RTEMS_BSP Timing Data Directive Times::
+* RTEMS_BSP Timing Data Task Manager::
+* RTEMS_BSP Timing Data Interrupt Manager::
+* RTEMS_BSP Timing Data Clock Manager::
+* RTEMS_BSP Timing Data Timer Manager::
+* RTEMS_BSP Timing Data Semaphore Manager::
+* RTEMS_BSP Timing Data Message Manager::
+* RTEMS_BSP Timing Data Event Manager::
+* RTEMS_BSP Timing Data Signal Manager::
+* RTEMS_BSP Timing Data Partition Manager::
+* RTEMS_BSP Timing Data Region Manager::
+* RTEMS_BSP Timing Data Dual-Ported Memory Manager::
+* RTEMS_BSP Timing Data I/O Manager::
+* RTEMS_BSP Timing Data Rate Monotonic Manager::
 @end menu
 @end ifinfo
 
 @ifinfo
-@node PPC603e Timing Data Introduction, PPC603e Timing Data Hardware Platform, PPC603e Timing Data, PPC603e Timing Data
+@node RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data, RTEMS_BSP Timing Data
 @end ifinfo
 @section Introduction
 
-The timing data for RTEMS on the PPC603e implementation
+The timing data for RTEMS on the RTEMS_BSP implementation
 of the PowerPC architecture is provided along with the target
 dependent aspects concerning the gathering of the timing data.
 The hardware platform used to gather the times is described to
@@ -53,7 +53,7 @@ latency and the context switch times as they pertain to the
 PowerPC version of RTEMS.
 
 @ifinfo
-@node PPC603e Timing Data Hardware Platform, PPC603e Timing Data Interrupt Latency, PPC603e Timing Data Introduction, PPC603e Timing Data
+@node RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data
 @end ifinfo
 @section Hardware Platform
 
@@ -74,7 +74,7 @@ although traps were enabled and the interrupt level of the
 PowerPC allows all interrupts.
 
 @ifinfo
-@node PPC603e Timing Data Interrupt Latency, PPC603e Timing Data Context Switch, PPC603e Timing Data Hardware Platform, PPC603e Timing Data
+@node RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data
 @end ifinfo
 @section Interrupt Latency
 
@@ -103,7 +103,7 @@ decrementer register.  This register was programmed to generate
 an interrupt after one countdown.
 
 @ifinfo
-@node PPC603e Timing Data Context Switch, PPC603e Timing Data Directive Times, PPC603e Timing Data Interrupt Latency, PPC603e Timing Data
+@node RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Directive Times, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data
 @end ifinfo
 @section Context Switch
 

doc/supplements/powerpc/timedata.t

@@ -12,38 +12,38 @@
 @end tex
 
 @ifinfo
-@node PPC603e Timing Data, PPC603e Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
+@node RTEMS_BSP Timing Data, RTEMS_BSP Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
 @end ifinfo
-@chapter PPC603e Timing Data
+@chapter RTEMS_BSP Timing Data
 @ifinfo
 @menu
-* PPC603e Timing Data Introduction::
-* PPC603e Timing Data Hardware Platform::
-* PPC603e Timing Data Interrupt Latency::
-* PPC603e Timing Data Context Switch::
-* PPC603e Timing Data Directive Times::
-* PPC603e Timing Data Task Manager::
-* PPC603e Timing Data Interrupt Manager::
-* PPC603e Timing Data Clock Manager::
-* PPC603e Timing Data Timer Manager::
-* PPC603e Timing Data Semaphore Manager::
-* PPC603e Timing Data Message Manager::
-* PPC603e Timing Data Event Manager::
-* PPC603e Timing Data Signal Manager::
-* PPC603e Timing Data Partition Manager::
-* PPC603e Timing Data Region Manager::
-* PPC603e Timing Data Dual-Ported Memory Manager::
-* PPC603e Timing Data I/O Manager::
-* PPC603e Timing Data Rate Monotonic Manager::
+* RTEMS_BSP Timing Data Introduction::
+* RTEMS_BSP Timing Data Hardware Platform::
+* RTEMS_BSP Timing Data Interrupt Latency::
+* RTEMS_BSP Timing Data Context Switch::
+* RTEMS_BSP Timing Data Directive Times::
+* RTEMS_BSP Timing Data Task Manager::
+* RTEMS_BSP Timing Data Interrupt Manager::
+* RTEMS_BSP Timing Data Clock Manager::
+* RTEMS_BSP Timing Data Timer Manager::
+* RTEMS_BSP Timing Data Semaphore Manager::
+* RTEMS_BSP Timing Data Message Manager::
+* RTEMS_BSP Timing Data Event Manager::
+* RTEMS_BSP Timing Data Signal Manager::
+* RTEMS_BSP Timing Data Partition Manager::
+* RTEMS_BSP Timing Data Region Manager::
+* RTEMS_BSP Timing Data Dual-Ported Memory Manager::
+* RTEMS_BSP Timing Data I/O Manager::
+* RTEMS_BSP Timing Data Rate Monotonic Manager::
 @end menu
 @end ifinfo
 
 @ifinfo
-@node PPC603e Timing Data Introduction, PPC603e Timing Data Hardware Platform, PPC603e Timing Data, PPC603e Timing Data
+@node RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data, RTEMS_BSP Timing Data
 @end ifinfo
 @section Introduction
 
-The timing data for RTEMS on the PPC603e implementation
+The timing data for RTEMS on the RTEMS_BSP implementation
 of the PowerPC architecture is provided along with the target
 dependent aspects concerning the gathering of the timing data.
 The hardware platform used to gather the times is described to
@@ -53,7 +53,7 @@ latency and the context switch times as they pertain to the
 PowerPC version of RTEMS.
 
 @ifinfo
-@node PPC603e Timing Data Hardware Platform, PPC603e Timing Data Interrupt Latency, PPC603e Timing Data Introduction, PPC603e Timing Data
+@node RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data
 @end ifinfo
 @section Hardware Platform
 
@@ -74,7 +74,7 @@ although traps were enabled and the interrupt level of the
 PowerPC allows all interrupts.
 
 @ifinfo
-@node PPC603e Timing Data Interrupt Latency, PPC603e Timing Data Context Switch, PPC603e Timing Data Hardware Platform, PPC603e Timing Data
+@node RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data
 @end ifinfo
 @section Interrupt Latency
 
@@ -103,7 +103,7 @@ decrementer register.  This register was programmed to generate
 an interrupt after one countdown.
 
 @ifinfo
-@node PPC603e Timing Data Context Switch, PPC603e Timing Data Directive Times, PPC603e Timing Data Interrupt Latency, PPC603e Timing Data
+@node RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Directive Times, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data
 @end ifinfo
 @section Context Switch
 

doc/supplements/powerpc/timedatadmv177.t

@@ -0,0 +1,139 @@
+@c
+@c  COPYRIGHT (c) 1988-1998.
+@c  On-Line Applications Research Corporation (OAR).
+@c  All rights reserved.
+@c
+@c  $Id$
+@c
+
+@include ../../common/timemac.texi
+@tex
+\global\advance \smallskipamount by -4pt
+@end tex
+
+@ifinfo
+@node DMV177 Timing Data, DMV177 Timing Data Introduction, PSIM Timing Data Rate Monotonic Manager, Top
+@end ifinfo
+@chapter DMV177 Timing Data
+@ifinfo
+@menu
+* DMV177 Timing Data Introduction::
+* DMV177 Timing Data Hardware Platform::
+* DMV177 Timing Data Interrupt Latency::
+* DMV177 Timing Data Context Switch::
+* DMV177 Timing Data Directive Times::
+* DMV177 Timing Data Task Manager::
+* DMV177 Timing Data Interrupt Manager::
+* DMV177 Timing Data Clock Manager::
+* DMV177 Timing Data Timer Manager::
+* DMV177 Timing Data Semaphore Manager::
+* DMV177 Timing Data Message Manager::
+* DMV177 Timing Data Event Manager::
+* DMV177 Timing Data Signal Manager::
+* DMV177 Timing Data Partition Manager::
+* DMV177 Timing Data Region Manager::
+* DMV177 Timing Data Dual-Ported Memory Manager::
+* DMV177 Timing Data I/O Manager::
+* DMV177 Timing Data Rate Monotonic Manager::
+@end menu
+@end ifinfo
+
+@ifinfo
+@node DMV177 Timing Data Introduction, DMV177 Timing Data Hardware Platform, DMV177 Timing Data, DMV177 Timing Data
+@end ifinfo
+@section Introduction
+
+The timing data for RTEMS on the DMV177 implementation
+of the PowerPC architecture is provided along with the target
+dependent aspects concerning the gathering of the timing data.
+The hardware platform used to gather the times is described to
+give the reader a better understanding of each directive time
+provided.  Also, provided is a description of the interrupt
+latency and the context switch times as they pertain to the
+PowerPC version of RTEMS.
+
+@ifinfo
+@node DMV177 Timing Data Hardware Platform, DMV177 Timing Data Interrupt Latency, DMV177 Timing Data Introduction, DMV177 Timing Data
+@end ifinfo
+@section Hardware Platform
+
+All times reported in this chapter were measured using the PowerPC
+Instruction Simulator (PSIM). PSIM simulates a variety of PowerPC
+6xx models with the DMV177 being used as the basis for the measurements
+reported in this chapter.
+
+The PowerPC decrementer register was was used to gather
+all timing information.  In real hardware implementations
+of the PowerPC architecture, this register would typically
+count something like CPU cycles or be a function of the clock
+speed.  However, wth PSIM each count of the decrementer register 
+represents an instruction.  Thus all measurements in this 
+chapter are reported as the actual number of instructions
+executed.  All sources of hardware interrupts were disabled,
+although traps were enabled and the interrupt level of the
+PowerPC allows all interrupts.
+
+@ifinfo
+@node DMV177 Timing Data Interrupt Latency, DMV177 Timing Data Context Switch, DMV177 Timing Data Hardware Platform, DMV177 Timing Data
+@end ifinfo
+@section Interrupt Latency
+
+The maximum period with traps disabled or the
+processor interrupt level set to it's highest value inside RTEMS
+is less than RTEMS_MAXIMUM_DISABLE_PERIOD
+microseconds including the instructions which
+disable and re-enable interrupts.  The time required for the
+PowerPC to vector an interrupt and for the RTEMS entry overhead
+before invoking the user's trap handler are a total of 
+RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
+microseconds.  These combine to yield a worst case interrupt
+latency of less than RTEMS_MAXIMUM_DISABLE_PERIOD +
+RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK microseconds at 
+RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz.
+[NOTE:  The maximum period with interrupts disabled was last
+determined for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
+
+The maximum period with interrupts disabled within
+RTEMS is hand-timed with some assistance from PSIM.  The maximum
+period with interrupts disabled with RTEMS occurs .... XXX
+
+The interrupt vector and entry overhead time was
+generated on the PSIM benchmark platform using the PowerPC's
+decrementer register.  This register was programmed to generate
+an interrupt after one countdown.
+
+@ifinfo
+@node DMV177 Timing Data Context Switch, DMV177 Timing Data Directive Times, DMV177 Timing Data Interrupt Latency, DMV177 Timing Data
+@end ifinfo
+@section Context Switch
+
+The RTEMS processor context switch time is XXX
+microseconds on the PSIM benchmark platform when no floating
+point context is saved or restored.  Additional execution time
+is required when a TASK_SWITCH user extension is configured.
+The use of the TASK_SWITCH extension is application dependent.
+Thus, its execution time is not considered part of the raw
+context switch time.
+
+Since RTEMS was designed specifically for embedded
+missile applications which are floating point intensive, the
+executive is optimized to avoid unnecessarily saving and
+restoring the state of the numeric coprocessor.  The state of
+the numeric coprocessor is only saved when an FLOATING_POINT
+task is dispatched and that task was not the last task to
+utilize the coprocessor.  In a system with only one
+FLOATING_POINT task, the state of the numeric coprocessor will
+never be saved or restored.  When the first FLOATING_POINT task
+is dispatched, RTEMS does not need to save the current state of
+the numeric coprocessor.
+
+The following table summarizes the context switch
+times for the PSIM benchmark platform:
+
+@include timetbldmv177.texi
+
+@tex
+\global\advance \smallskipamount by 4pt
+@end tex
+
+