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Added mc68681 stuff to the makefile.

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Added numerous constants to mc68681_p.h.

Changed spacing.

At this point the polled support is in but nothing else is right except the
structure.
This commit is contained in:
Joel Sherrill
1998-06-22 11:09:32 +00:00
parent 36152b0e4b
commit ab2dbd7e94
8 changed files with 688 additions and 180 deletions
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4
c/src/lib/libchip/serial/Makefile.in
View File

@@ -11,11 +11,11 @@ PROJECT_ROOT = @PROJECT_ROOT@
LIBNAME=libserialio.a
LIB=${ARCH}/${LIBNAME}
C_PIECES=ns16550 z85c30
C_PIECES=mc68681 ns16550 z85c30
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
INSTALLED_H_FILES=$(srcdir)/ns16550.h $(srcdir)/z85c30.h \
INSTALLED_H_FILES=$(srcdir)/mc68681.h $(srcdir)/ns16550.h $(srcdir)/z85c30.h \
$(srcdir)/serial.h
SRCS=$(C_FILES) $(H_FILES) $(SYS_H_FILES) $(RTEMS_H_FILES) $(PRIVATE_H_FILES)
OBJS=$(C_O_FILES)

178
c/src/lib/libchip/serial/mc68681.c
View File

@@ -24,6 +24,7 @@
#include <libchip/serial.h>
#include "mc68681_p.h"
#include "mc68681.h"
/*
* Flow control is only supported when using interrupts
@@ -67,13 +68,6 @@ console_fns mc68681_fns_polled =
extern void set_vector( rtems_isr_entry, rtems_vector_number, int );
/*
* Types for get and set register routines
*/
typedef unsigned8 (*getRegister_f)(unsigned32 port, unsigned8 register);
typedef void (*setRegister_f)(
unsigned32 port, unsigned8 reg, unsigned8 value);
/*
* Console Device Driver Entry Points
*/
@@ -81,7 +75,7 @@ typedef void (*setRegister_f)(
static boolean mc68681_probe(int minor)
{
/*
* If the configuration dependant probe has located the device then
* If the configuration dependent probe has located the device then
* assume it is there
*/
return(TRUE);
@@ -89,63 +83,71 @@ static boolean mc68681_probe(int minor)
static void mc68681_init(int minor)
{
/* XXX */
unsigned32 pMC68681;
unsigned8 ucTrash;
unsigned8 ucDataByte;
unsigned32 ulBaudDivisor;
mc68681_context *pns68681Context;
mc68681_context *pmc68681Context;
setRegister_f setReg;
getRegister_f getReg;
pmc68681Context=(ns68681_context *)malloc(sizeof(mc68681_context));
#if 1
ulBaudDivisor = ucDataByte = ucTrash = 0;
#endif
pmc68681Context = (mc68681_context *) malloc(sizeof(mc68681_context));
Console_Port_Data[minor].pDeviceContext=(void *)pmc68681Context;
pmc68681Context->ucModemCtrl=SP_MODEM_IRQ;
Console_Port_Data[minor].pDeviceContext = (void *)pmc68681Context;
#if 0
pmc68681Context->ucModemCtrl = SP_MODEM_IRQ;
#endif
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
getReg = Console_Port_Tbl[minor].getRegister;
#if 0
/* Clear the divisor latch, clear all interrupt enables,
* and reset and
* disable the FIFO's.
*/
(*setReg)(pMC68681, NS68681_LINE_CONTROL, 0x0);
(*setReg)(pMC68681, NS68681_INTERRUPT_ENABLE, 0x0);
(*setReg)(pMC68681, MC68681_LINE_CONTROL, 0x0);
(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, 0x0);
/* Set the divisor latch and set the baud rate. */
ulBaudDivisor=MC68681_Baud((unsigned32)Console_Port_Tbl[minor].pDeviceParams);
ucDataByte = SP_LINE_DLAB;
(*setReg)(pMC68681, NS68681_LINE_CONTROL, ucDataByte);
(*setReg)(pMC68681, NS68681_TRANSMIT_BUFFER, ulBaudDivisor&0xff);
(*setReg)(pMC68681, NS68681_INTERRUPT_ENABLE, (ulBaudDivisor>>8)&0xff);
(*setReg)(pMC68681, MC68681_LINE_CONTROL, ucDataByte);
(*setReg)(pMC68681, MC68681_TRANSMIT_BUFFER, ulBaudDivisor&0xff);
(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, (ulBaudDivisor>>8)&0xff);
/* Clear the divisor latch and set the character size to eight bits */
/* with one stop bit and no parity checking. */
ucDataByte = EIGHT_BITS;
(*setReg)(pMC68681, NS68681_LINE_CONTROL, ucDataByte);
(*setReg)(pMC68681, MC68681_LINE_CONTROL, ucDataByte);
/* Enable and reset transmit and receive FIFOs. TJA */
ucDataByte = SP_FIFO_ENABLE;
(*setReg)(pMC68681, NS68681_FIFO_CONTROL, ucDataByte);
(*setReg)(pMC68681, MC68681_FIFO_CONTROL, ucDataByte);
ucDataByte = SP_FIFO_ENABLE | SP_FIFO_RXRST | SP_FIFO_TXRST;
(*setReg)(pMC68681, NS68681_FIFO_CONTROL, ucDataByte);
(*setReg)(pMC68681, MC68681_FIFO_CONTROL, ucDataByte);
/*
* Disable interrupts
*/
ucDataByte = 0;
(*setReg)(pMC68681, NS68681_INTERRUPT_ENABLE, ucDataByte);
(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, ucDataByte);
/* Set data terminal ready. */
/* And open interrupt tristate line */
(*setReg)(pMC68681, NS68681_MODEM_CONTROL,pmc68681Context->ucModemCtrl);
(*setReg)(pMC68681, MC68681_MODEM_CONTROL,pmc68681Context->ucModemCtrl);
ucTrash = (*getReg)(pMC68681, NS68681_LINE_STATUS );
ucTrash = (*getReg)(pMC68681, NS68681_RECEIVE_BUFFER );
ucTrash = (*getReg)(pMC68681, MC68681_LINE_STATUS );
ucTrash = (*getReg)(pMC68681, MC68681_RECEIVE_BUFFER );
#endif
}
static int mc68681_open(
@@ -154,6 +156,7 @@ static int mc68681_open(
void * arg
)
{
/* XXX */
/*
* Assert DTR
*/
@@ -171,6 +174,7 @@ static int mc68681_close(
void * arg
)
{
/* XXX */
/*
* Negate DTR
*/
@@ -194,25 +198,27 @@ static void mc68681_write_polled(
unsigned char ucLineStatus;
int iTimeout;
getRegister_f getReg;
setRegister_f setReg;
setData_f setData;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
getReg = Console_Port_Tbl[minor].getRegister;
setReg = Console_Port_Tbl[minor].setRegister;
setData = Console_Port_Tbl[minor].setData;
/*
* wait for transmitter holding register to be empty
*/
iTimeout=1000;
ucLineStatus = (*getReg)(pMC68681, NS68681_LINE_STATUS);
while ((ucLineStatus & SP_LSR_THOLD) == 0) {
iTimeout = 1000;
ucLineStatus = (*getReg)(pMC68681, MC68681_STATUS_REG);
while ((ucLineStatus & MC68681_TX_READY) == 0) {
/*
* Yield while we wait
*/
if(_System_state_Is_up(_System_state_Get())) {
rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
}
ucLineStatus = (*getReg)(pMC68681, NS68681_LINE_STATUS);
ucLineStatus = (*getReg)(pMC68681, MC68681_STATUS_REG);
if(!--iTimeout) {
break;
}
@@ -221,23 +227,29 @@ static void mc68681_write_polled(
/*
* transmit character
*/
(*setReg)(pMC68681, NS68681_TRANSMIT_BUFFER, cChar);
(*setData)(pMC68681, cChar);
}
/*
* These routines provide control of the RTS and DTR lines
*/
/*
* mc68681_assert_RTS
*/
static int mc68681_assert_RTS(int minor)
{
/* XXX */
unsigned32 pMC68681;
unsigned32 Irql;
mc68681_context *pns68681Context;
mc68681_context *pmc68681Context;
setRegister_f setReg;
pmc68681Context=(ns68681_context *) Console_Port_Data[minor].pDeviceContext;
pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
@@ -246,8 +258,10 @@ static int mc68681_assert_RTS(int minor)
* Assert RTS
*/
rtems_interrupt_disable(Irql);
pmc68681Context->ucModemCtrl|=SP_MODEM_RTS;
(*setReg)(pMC68681, NS68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#if 0
pmc68681Context->ucModemCtrl |= SP_MODEM_RTS;
(*setReg)(pMC68681, MC68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#endif
rtems_interrupt_enable(Irql);
return 0;
}
@@ -257,12 +271,13 @@ static int mc68681_assert_RTS(int minor)
*/
static int mc68681_negate_RTS(int minor)
{
/* XXX */
unsigned32 pMC68681;
unsigned32 Irql;
mc68681_context *pns68681Context;
mc68681_context *pmc68681Context;
setRegister_f setReg;
pmc68681Context=(ns68681_context *) Console_Port_Data[minor].pDeviceContext;
pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
@@ -271,8 +286,10 @@ static int mc68681_negate_RTS(int minor)
* Negate RTS
*/
rtems_interrupt_disable(Irql);
pmc68681Context->ucModemCtrl&=~SP_MODEM_RTS;
(*setReg)(pMC68681, NS68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#if 0
pmc68681Context->ucModemCtrl &= ~SP_MODEM_RTS;
(*setReg)(pMC68681, MC68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#endif
rtems_interrupt_enable(Irql);
return 0;
}
@@ -281,17 +298,20 @@ static int mc68681_negate_RTS(int minor)
* These flow control routines utilise a connection from the local DTR
* line to the remote CTS line
*/
/*
* mc68681_assert_DTR
*/
static int mc68681_assert_DTR(int minor)
{
/* XXX */
unsigned32 pMC68681;
unsigned32 Irql;
mc68681_context *pns68681Context;
mc68681_context *pmc68681Context;
setRegister_f setReg;
pmc68681Context=(ns68681_context *) Console_Port_Data[minor].pDeviceContext;
pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
@@ -300,8 +320,10 @@ static int mc68681_assert_DTR(int minor)
* Assert DTR
*/
rtems_interrupt_disable(Irql);
pmc68681Context->ucModemCtrl|=SP_MODEM_DTR;
(*setReg)(pMC68681, NS68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#if 0
pmc68681Context->ucModemCtrl |= SP_MODEM_DTR;
(*setReg)(pMC68681, MC68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#endif
rtems_interrupt_enable(Irql);
return 0;
}
@@ -309,14 +331,16 @@ static int mc68681_assert_DTR(int minor)
/*
* mc68681_negate_DTR
*/
static int mc68681_negate_DTR(int minor)
{
/* XXX */
unsigned32 pMC68681;
unsigned32 Irql;
mc68681_context *pns68681Context;
mc68681_context *pmc68681Context;
setRegister_f setReg;
pmc68681Context=(ns68681_context *) Console_Port_Data[minor].pDeviceContext;
pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
@@ -325,8 +349,10 @@ static int mc68681_negate_DTR(int minor)
* Negate DTR
*/
rtems_interrupt_disable(Irql);
pmc68681Context->ucModemCtrl&=~SP_MODEM_DTR;
(*setReg)(pMC68681, NS68681_MODEM_CONTROL,pmc68681Context->ucModemCtrl);
#if 0
pmc68681Context->ucModemCtrl &= ~SP_MODEM_DTR;
(*setReg)(pMC68681, MC68681_MODEM_CONTROL,pmc68681Context->ucModemCtrl);
#endif
rtems_interrupt_enable(Irql);
return 0;
}
@@ -334,7 +360,7 @@ static int mc68681_negate_DTR(int minor)
/*
* mc68681_isr
*
* This routine is the console interrupt handler for COM1 and COM2
* This routine is the console interrupt handler.
*
* Input parameters:
* vector - vector number
@@ -348,6 +374,7 @@ static void mc68681_process(
int minor
)
{
/* XXX */
unsigned32 pMC68681;
volatile unsigned8 ucLineStatus;
volatile unsigned8 ucInterruptId;
@@ -355,20 +382,24 @@ static void mc68681_process(
getRegister_f getReg;
setRegister_f setReg;
#if 1
cChar = ucInterruptId = ucLineStatus = 0;
#endif
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
getReg = Console_Port_Tbl[minor].getRegister;
setReg = Console_Port_Tbl[minor].setRegister;
#if 0
do {
/*
* Deal with any received characters
*/
while(TRUE) {
ucLineStatus = (*getReg)(pMC68681, NS68681_LINE_STATUS);
ucLineStatus = (*getReg)(pMC68681, MC68681_LINE_STATUS);
if(~ucLineStatus & SP_LSR_RDY) {
break;
}
cChar = (*getReg)(pMC68681, NS68681_RECEIVE_BUFFER);
cChar = (*getReg)(pMC68681, MC68681_RECEIVE_BUFFER);
rtems_termios_enqueue_raw_characters(
Console_Port_Data[minor].termios_data,
&cChar,
@@ -378,8 +409,8 @@ static void mc68681_process(
while(TRUE) {
if(Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) {
Console_Port_Data[minor].bActive=FALSE;
if(Console_Port_Tbl[minor].pDeviceFlow !=&mc68681_flow_RTSCTS) {
Console_Port_Data[minor].bActive = FALSE;
if(Console_Port_Tbl[minor].pDeviceFlow != &mc68681_flow_RTSCTS) {
mc68681_negate_RTS(minor);
}
@@ -389,7 +420,7 @@ static void mc68681_process(
break;
}
ucLineStatus = (*getReg)(pMC68681, NS68681_LINE_STATUS);
ucLineStatus = (*getReg)(pMC68681, MC68681_LINE_STATUS);
if(~ucLineStatus & SP_LSR_THOLD) {
/*
* We'll get another interrupt when
@@ -403,12 +434,13 @@ static void mc68681_process(
/*
* transmit character
*/
(*setReg)(pMC68681, NS68681_TRANSMIT_BUFFER, cChar);
(*setReg)(pMC68681, MC68681_TRANSMIT_BUFFER, cChar);
}
ucInterruptId = (*getReg)(pMC68681, NS68681_INTERRUPT_ID);
ucInterruptId = (*getReg)(pMC68681, MC68681_INTERRUPT_ID);
}
while((ucInterruptId&0xf)!=0x1);
while((ucInterruptId&0xf) != 0x1);
#endif
}
static rtems_isr mc68681_isr(
@@ -417,8 +449,8 @@ static rtems_isr mc68681_isr(
{
int minor;
for(minor=0;minor<Console_Port_Count;minor++) {
if(vector==Console_Port_Tbl[minor].ulIntVector) {
for(minor=0 ; minor<Console_Port_Count ; minor++) {
if(vector == Console_Port_Tbl[minor].ulIntVector) {
mc68681_process(minor);
}
}
@@ -427,6 +459,7 @@ static rtems_isr mc68681_isr(
/*
* mc68681_flush
*/
static int mc68681_flush(int major, int minor, void *arg)
{
while(!Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) {
@@ -460,19 +493,24 @@ static void mc68681_enable_interrupts(
int minor
)
{
/* XXX */
unsigned32 pMC68681;
unsigned8 ucDataByte;
setRegister_f setReg;
setRegister_f setReg;
#if 1
ucDataByte = 0;
#endif
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
#if 0
/*
* Enable interrupts
*/
ucDataByte = SP_INT_RX_ENABLE | SP_INT_TX_ENABLE;
(*setReg)(pMC68681, NS68681_INTERRUPT_ENABLE, ucDataByte);
(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, ucDataByte);
#endif
}
static void mc68681_initialize_interrupts(int minor)
@@ -492,8 +530,8 @@ static void mc68681_initialize_interrupts(int minor)
* mc68681_write_support_int
*
* Console Termios output entry point.
*
*/
static int mc68681_write_support_int(
int minor,
const char *buf,
@@ -503,7 +541,7 @@ static int mc68681_write_support_int(
int i;
unsigned32 Irql;
for(i=0; i<len;) {
for(i=0 ; i<len ;) {
if(Ring_buffer_Is_full(&Console_Port_Data[minor].TxBuffer)) {
if(!Console_Port_Data[minor].bActive) {
/*
@@ -537,13 +575,14 @@ static int mc68681_write_support_int(
/*
* Ensure that characters are on the way
*/
if(!Console_Port_Data[minor].bActive) {
/*
* Wake up the device
*/
rtems_interrupt_disable(Irql);
Console_Port_Data[minor].bActive = TRUE;
if(Console_Port_Tbl[minor].pDeviceFlow !=&mc68681_flow_RTSCTS) {
if(Console_Port_Tbl[minor].pDeviceFlow != &mc68681_flow_RTSCTS) {
mc68681_assert_RTS(minor);
}
mc68681_process(minor);
@@ -559,6 +598,7 @@ static int mc68681_write_support_int(
* Console Termios output entry point.
*
*/
static int mc68681_write_support_polled(
int minor,
const char *buf,
@@ -598,14 +638,16 @@ static int mc68681_inbyte_nonblocking_polled(
unsigned char ucLineStatus;
char cChar;
getRegister_f getReg;
getData_f getData;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
getReg = Console_Port_Tbl[minor].getRegister;
getData = Console_Port_Tbl[minor].getData;
ucLineStatus = (*getReg)(pMC68681, NS68681_LINE_STATUS);
if(ucLineStatus & SP_LSR_RDY) {
cChar = (*getReg)(pMC68681, NS68681_RECEIVE_BUFFER);
return((int)cChar);
ucLineStatus = (*getReg)(pMC68681, MC68681_STATUS_REG);
if(ucLineStatus & MC68681_RX_READY) {
cChar = (*getData)(pMC68681);
return (int)cChar;
} else {
return(-1);
}

9
c/src/lib/libchip/serial/mc68681.h
View File

@@ -18,15 +18,24 @@
extern "C" {
#endif
/*
* These are just used in the interface between this driver and
* the read/write register routines.
*/
#define MC68681_STATUS_REG 0xFF
/*
* Driver function table
*/
extern console_fns mc68681_fns;
extern console_fns mc68681_fns_polled;
/*
* Flow control function tables
*/
extern console_flow mc68681_flow_RTSCTS;
extern console_flow mc68681_flow_DTRCTS;

243
c/src/lib/libchip/serial/mc68681_p.h
View File

@@ -18,6 +18,209 @@
extern "C" {
#endif
/*
* mc68681 register offsets Read/Write Addresses
*/
#define MC68681_MODE_REG_1A 0 /* MR1A-MR Prior to Read */
#define MC68681_MODE_REG_2A 0 /* MR2A-MR After Read */
#define MC68681_COUNT_MODE_CURRENT_MSB 6 /* CTU */
#define MC68681_COUNTER_TIMER_UPPER_REG 6 /* CTU */
#define MC68681_COUNT_MODE_CURRENT_LSB 7 /* CTL */
#define MC68681_COUNTER_TIMER_LOWER_REG 7 /* CTL */
#define MC68681_INTERRUPT_VECTOR_REG 12 /* IVR */
#define MC68681_MODE_REG_1B 8 /* MR1B-MR Prior to Read */
#define MC68681_MODE_REG_2B 8 /* MR2BA-MR After Read */
/*
* mc68681 register offsets Read Only Addresses
*/
#define MC68681_STATUS_REG_A 1 /* SRA */
#define MC68681_MASK_ISR_REG 2 /* MISR */
#define MC68681_RECEIVE_BUFFER_A 3 /* RHRA */
#define MC68681_INPUT_PORT_CHANGE_REG 4 /* IPCR */
#define MC68681_INTERRUPT_STATUS_REG 5 /* ISR */
#define MC68681_STATUS_REG_B 9 /* SRB */
#define MC68681_RECEIVE_BUFFER_B 11 /* RHRB */
#define MC68681_INPUT_PORT 13 /* IP */
#define MC68681_START_COUNT_CMD 14 /* SCC */
#define MC68681_STOP_COUNT_CMD 15 /* STC */
/*
* mc68681 register offsets Write Only Addresses
*/
#define MC68681_CLOCK_SELECT_REG_A 1 /* CSRA */
#define MC68681_COMMAND_REG_A 2 /* CRA */
#define MC68681_TRANSMIT_BUFFER_A 3 /* THRA */
#define MC68681_AUX_CTRL_REG 4 /* ACR */
#define MC68681_INTERRUPT_MASK_REG 5 /* IMR */
#define MC68681_CLOCK_SELECT_REG_B 9 /* CSRB */
#define MC68681_COMMAND_REG_B 10 /* CRB */
#define MC68681_TRANSMIT_BUFFER_B 11 /* THRB */
#define MC68681_OUTPUT_PORT_CONFIG_REG 13 /* OPCR */
#define MC68681_OUTPUT_PORT_SET_REG 14 /* SOPBC */
#define MC68681_OUTPUT_PORT_RESET_BITS 15 /* COPBC */
/*
* DUART Command Register Definitions:
*
* MC68681_COMMAND_REG_A,MC68681_COMMAND_REG_B
*/
#define MC68681_MODE_REG_ENABLE_RX 0x01
#define MC68681_MODE_REG_DISABLE_RX 0x02
#define MC68681_MODE_REG_ENABLE_TX 0x04
#define MC68681_MODE_REG_DISABLE_TX 0x08
#define MC68681_MODE_REG_RESET_MR_PTR 0x10
#define MC68681_MODE_REG_RESET_RX 0x20
#define MC68681_MODE_REG_RESET_TX 0x30
#define MC68681_MODE_REG_RESET_ERROR 0x40
#define MC68681_MODE_REG_RESET_BREAK 0x50
#define MC68681_MODE_REG_START_BREAK 0x60
#define MC68681_MODE_REG_STOP_BREAK 0x70
#define MC68681_MODE_REG_SET_RX_BRG 0x80
#define MC68681_MODE_REG_CLEAR_RX_BRG 0x90
#define MC68681_MODE_REG_SET_TX_BRG 0xa0
#define MC68681_MODE_REG_CLEAR_TX_BRG 0xb0
#define MC68681_MODE_REG_SET_STANDBY 0xc0
#define MC68681_MODE_REG_SET_ACTIVE 0xd0
/*
* Mode Register Definitions
*
* MC68681_MODE_REG_1A
* MC68681_MODE_REG_1B
*/
#define MC68681_5BIT_CHARS 0x00
#define MC68681_6BIT_CHARS 0x01
#define MC68681_7BIT_CHARS 0x02
#define MC68681_8BIT_CHARS 0x03
#define MC68681_ODD_PARITY 0x00
#define MC68681_EVEN_PARITY 0x04
#define MC68681_WITH_PARITY 0x00
#define MC68681_FORCE_PARITY 0x08
#define MC68681_NO_PARITY 0x10
#define MC68681_MULTI_DROP 0x18
#define MC68681_ERR_MODE_CHAR 0x00
#define MC68681_ERR_MODE_BLOCK 0x20
#define MC68681_RX_INTR_RX_READY 0x00
#define MC68681_RX_INTR_FFULL 0x40
#define MC68681_NO_RX_RTS_CTL 0x00
#define MC68681_RX_RTS_CTRL 0x80
/*
* Mode Register Definitions
*
* MC68681_MODE_REG_2A
* MC68681_MODE_REG_2B
*/
#define MC68681_STOP_BIT_LENGTH__563 0x00
#define MC68681_STOP_BIT_LENGTH__625 0x01
#define MC68681_STOP_BIT_LENGTH__688 0x02
#define MC68681_STOP_BIT_LENGTH__75 0x03
#define MC68681_STOP_BIT_LENGTH__813 0x04
#define MC68681_STOP_BIT_LENGTH__875 0x05
#define MC68681_STOP_BIT_LENGTH__938 0x06
#define MC68681_STOP_BIT_LENGTH_1 0x07
#define MC68681_STOP_BIT_LENGTH_1_563 0x08
#define MC68681_STOP_BIT_LENGTH_1_625 0x09
#define MC68681_STOP_BIT_LENGTH_1_688 0x0a
#define MC68681_STOP_BIT_LENGTH_1_75 0x0b
#define MC68681_STOP_BIT_LENGTH_1_813 0x0c
#define MC68681_STOP_BIT_LENGTH_1_875 0x0d
#define MC68681_STOP_BIT_LENGTH_1_938 0x0e
#define MC68681_STOP_BIT_LENGTH_2 0x0f
#define MC68681_CTS_ENABLE_TX 0x10
#define MC68681_TX_RTS_CTRL 0x20
#define MC68681_CHANNEL_MODE_NORMAL 0x00
#define MC68681_CHANNEL_MODE_ECHO 0x40
#define MC68681_CHANNEL_MODE_LOCAL_LOOP 0x80
#define MC68681_CHANNEL_MODE_REMOTE_LOOP 0xc0
/*
* Status Register Definitions
*
* MC68681_STATUS_REG_A, MC68681_STATUS_REG_B
*/
#define MC68681_RX_READY 0x01
#define MC68681_FFULL 0x02
#define MC68681_TX_READY 0x04
#define MC68681_TX_EMPTY 0x08
#define MC68681_OVERRUN_ERROR 0x10
#define MC68681_PARITY_ERROR 0x20
#define MC68681_FRAMING_ERROR 0x40
#define MC68681_RECEIVED_BREAK 0x80
/*
* Interupt Status Register Definitions.
*
* MC68681_INTERRUPT_STATUS_REG
*/
/*
* Interupt Mask Register Definitions
*
* MC68681_INTERRUPT_MASK_REG
*/
#define MC68681_IR_TX_READY_A 0x01
#define MC68681_IR_RX_READY_A 0x02
#define MC68681_IR_BREAK_A 0x04
#define MC68681_IR_COUNTER_READY 0x08
#define MC68681_IR_TX_READY_B 0x10
#define MC68681_IR_RX_READY_B 0x20
#define MC68681_IR_BREAK_B 0x40
#define MC68681_IR_INPUT_PORT_CHANGE 0x80
/*
* Status Register Definitions.
*
* MC68681_STATUS_REG_A,MC68681_STATUS_REG_B
*/
#define MC68681_STATUS_RXRDY 0x01
#define MC68681_STATUS_FFULL 0x02
#define MC68681_STATUS_TXRDY 0x04
#define MC68681_STATUS_TXEMT 0x08
#define MC68681_STATUS_OVERRUN_ERROR 0x10
#define MC68681_STATUS_PARITY_ERROR 0x20
#define MC68681_STATUS_FRAMING_ERROR 0x40
#define MC68681_STATUS_RECEIVED_BREAK 0x80
/*
* Definitions for the Interrupt Vector Register:
*
* MC68681_INTERRUPT_VECTOR_REG
*/
#define MC68681_INTERRUPT_VECTOR_INIT 0x0f
/*
* Definitions for the Auxiliary Control Register
*
* MC68681_AUX_CTRL_REG
*/
#define MC68681_AUX_BRG_SET1 0x00
#define MC68681_AUX_BRG_SET2 0x80
/*
* Per chip context control
*/
typedef struct _mc68681_context
{
@@ -32,36 +235,36 @@ static boolean mc68681_probe(int minor);
static void mc68681_init(int minor);
static int mc68681_open(
int major,
int minor,
void * arg
int major,
int minor,
void * arg
);
static int mc68681_close(
int major,
int minor,
void * arg
int major,
int minor,
void * arg
);
static void mc68681_write_polled(
int minor,
char cChar
int minor,
char cChar
);
static int mc68681_assert_RTS(
int minor
int minor
);
static int mc68681_negate_RTS(
int minor
int minor
);
static int mc68681_assert_DTR(
int minor
int minor
);
static int mc68681_negate_DTR(
int minor
int minor
);
static void mc68681_initialize_interrupts(int minor);
@@ -69,19 +272,19 @@ static void mc68681_initialize_interrupts(int minor);
static int mc68681_flush(int major, int minor, void *arg);
static int mc68681_write_support_int(
int minor,
const char *buf,
int len
int minor,
const char *buf,
int len
);
static int mc68681_write_support_polled(
int minor,
const char *buf,
int len
);
int minor,
const char *buf,
int len
);
static int mc68681_inbyte_nonblocking_polled(
int minor
int minor
);
#ifdef __cplusplus

4
c/src/libchip/serial/Makefile.in
View File

@@ -11,11 +11,11 @@ PROJECT_ROOT = @PROJECT_ROOT@
LIBNAME=libserialio.a
LIB=${ARCH}/${LIBNAME}
C_PIECES=ns16550 z85c30
C_PIECES=mc68681 ns16550 z85c30
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
INSTALLED_H_FILES=$(srcdir)/ns16550.h $(srcdir)/z85c30.h \
INSTALLED_H_FILES=$(srcdir)/mc68681.h $(srcdir)/ns16550.h $(srcdir)/z85c30.h \
$(srcdir)/serial.h
SRCS=$(C_FILES) $(H_FILES) $(SYS_H_FILES) $(RTEMS_H_FILES) $(PRIVATE_H_FILES)
OBJS=$(C_O_FILES)

178
c/src/libchip/serial/mc68681.c
View File

@@ -24,6 +24,7 @@
#include <libchip/serial.h>
#include "mc68681_p.h"
#include "mc68681.h"
/*
* Flow control is only supported when using interrupts
@@ -67,13 +68,6 @@ console_fns mc68681_fns_polled =
extern void set_vector( rtems_isr_entry, rtems_vector_number, int );
/*
* Types for get and set register routines
*/
typedef unsigned8 (*getRegister_f)(unsigned32 port, unsigned8 register);
typedef void (*setRegister_f)(
unsigned32 port, unsigned8 reg, unsigned8 value);
/*
* Console Device Driver Entry Points
*/
@@ -81,7 +75,7 @@ typedef void (*setRegister_f)(
static boolean mc68681_probe(int minor)
{
/*
* If the configuration dependant probe has located the device then
* If the configuration dependent probe has located the device then
* assume it is there
*/
return(TRUE);
@@ -89,63 +83,71 @@ static boolean mc68681_probe(int minor)
static void mc68681_init(int minor)
{
/* XXX */
unsigned32 pMC68681;
unsigned8 ucTrash;
unsigned8 ucDataByte;
unsigned32 ulBaudDivisor;
mc68681_context *pns68681Context;
mc68681_context *pmc68681Context;
setRegister_f setReg;
getRegister_f getReg;
pmc68681Context=(ns68681_context *)malloc(sizeof(mc68681_context));
#if 1
ulBaudDivisor = ucDataByte = ucTrash = 0;
#endif
pmc68681Context = (mc68681_context *) malloc(sizeof(mc68681_context));
Console_Port_Data[minor].pDeviceContext=(void *)pmc68681Context;
pmc68681Context->ucModemCtrl=SP_MODEM_IRQ;
Console_Port_Data[minor].pDeviceContext = (void *)pmc68681Context;
#if 0
pmc68681Context->ucModemCtrl = SP_MODEM_IRQ;
#endif
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
getReg = Console_Port_Tbl[minor].getRegister;
#if 0
/* Clear the divisor latch, clear all interrupt enables,
* and reset and
* disable the FIFO's.
*/
(*setReg)(pMC68681, NS68681_LINE_CONTROL, 0x0);
(*setReg)(pMC68681, NS68681_INTERRUPT_ENABLE, 0x0);
(*setReg)(pMC68681, MC68681_LINE_CONTROL, 0x0);
(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, 0x0);
/* Set the divisor latch and set the baud rate. */
ulBaudDivisor=MC68681_Baud((unsigned32)Console_Port_Tbl[minor].pDeviceParams);
ucDataByte = SP_LINE_DLAB;
(*setReg)(pMC68681, NS68681_LINE_CONTROL, ucDataByte);
(*setReg)(pMC68681, NS68681_TRANSMIT_BUFFER, ulBaudDivisor&0xff);
(*setReg)(pMC68681, NS68681_INTERRUPT_ENABLE, (ulBaudDivisor>>8)&0xff);
(*setReg)(pMC68681, MC68681_LINE_CONTROL, ucDataByte);
(*setReg)(pMC68681, MC68681_TRANSMIT_BUFFER, ulBaudDivisor&0xff);
(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, (ulBaudDivisor>>8)&0xff);
/* Clear the divisor latch and set the character size to eight bits */
/* with one stop bit and no parity checking. */
ucDataByte = EIGHT_BITS;
(*setReg)(pMC68681, NS68681_LINE_CONTROL, ucDataByte);
(*setReg)(pMC68681, MC68681_LINE_CONTROL, ucDataByte);
/* Enable and reset transmit and receive FIFOs. TJA */
ucDataByte = SP_FIFO_ENABLE;
(*setReg)(pMC68681, NS68681_FIFO_CONTROL, ucDataByte);
(*setReg)(pMC68681, MC68681_FIFO_CONTROL, ucDataByte);
ucDataByte = SP_FIFO_ENABLE | SP_FIFO_RXRST | SP_FIFO_TXRST;
(*setReg)(pMC68681, NS68681_FIFO_CONTROL, ucDataByte);
(*setReg)(pMC68681, MC68681_FIFO_CONTROL, ucDataByte);
/*
* Disable interrupts
*/
ucDataByte = 0;
(*setReg)(pMC68681, NS68681_INTERRUPT_ENABLE, ucDataByte);
(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, ucDataByte);
/* Set data terminal ready. */
/* And open interrupt tristate line */
(*setReg)(pMC68681, NS68681_MODEM_CONTROL,pmc68681Context->ucModemCtrl);
(*setReg)(pMC68681, MC68681_MODEM_CONTROL,pmc68681Context->ucModemCtrl);
ucTrash = (*getReg)(pMC68681, NS68681_LINE_STATUS );
ucTrash = (*getReg)(pMC68681, NS68681_RECEIVE_BUFFER );
ucTrash = (*getReg)(pMC68681, MC68681_LINE_STATUS );
ucTrash = (*getReg)(pMC68681, MC68681_RECEIVE_BUFFER );
#endif
}
static int mc68681_open(
@@ -154,6 +156,7 @@ static int mc68681_open(
void * arg
)
{
/* XXX */
/*
* Assert DTR
*/
@@ -171,6 +174,7 @@ static int mc68681_close(
void * arg
)
{
/* XXX */
/*
* Negate DTR
*/
@@ -194,25 +198,27 @@ static void mc68681_write_polled(
unsigned char ucLineStatus;
int iTimeout;
getRegister_f getReg;
setRegister_f setReg;
setData_f setData;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
getReg = Console_Port_Tbl[minor].getRegister;
setReg = Console_Port_Tbl[minor].setRegister;
setData = Console_Port_Tbl[minor].setData;
/*
* wait for transmitter holding register to be empty
*/
iTimeout=1000;
ucLineStatus = (*getReg)(pMC68681, NS68681_LINE_STATUS);
while ((ucLineStatus & SP_LSR_THOLD) == 0) {
iTimeout = 1000;
ucLineStatus = (*getReg)(pMC68681, MC68681_STATUS_REG);
while ((ucLineStatus & MC68681_TX_READY) == 0) {
/*
* Yield while we wait
*/
if(_System_state_Is_up(_System_state_Get())) {
rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
}
ucLineStatus = (*getReg)(pMC68681, NS68681_LINE_STATUS);
ucLineStatus = (*getReg)(pMC68681, MC68681_STATUS_REG);
if(!--iTimeout) {
break;
}
@@ -221,23 +227,29 @@ static void mc68681_write_polled(
/*
* transmit character
*/
(*setReg)(pMC68681, NS68681_TRANSMIT_BUFFER, cChar);
(*setData)(pMC68681, cChar);
}
/*
* These routines provide control of the RTS and DTR lines
*/
/*
* mc68681_assert_RTS
*/
static int mc68681_assert_RTS(int minor)
{
/* XXX */
unsigned32 pMC68681;
unsigned32 Irql;
mc68681_context *pns68681Context;
mc68681_context *pmc68681Context;
setRegister_f setReg;
pmc68681Context=(ns68681_context *) Console_Port_Data[minor].pDeviceContext;
pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
@@ -246,8 +258,10 @@ static int mc68681_assert_RTS(int minor)
* Assert RTS
*/
rtems_interrupt_disable(Irql);
pmc68681Context->ucModemCtrl|=SP_MODEM_RTS;
(*setReg)(pMC68681, NS68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#if 0
pmc68681Context->ucModemCtrl |= SP_MODEM_RTS;
(*setReg)(pMC68681, MC68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#endif
rtems_interrupt_enable(Irql);
return 0;
}
@@ -257,12 +271,13 @@ static int mc68681_assert_RTS(int minor)
*/
static int mc68681_negate_RTS(int minor)
{
/* XXX */
unsigned32 pMC68681;
unsigned32 Irql;
mc68681_context *pns68681Context;
mc68681_context *pmc68681Context;
setRegister_f setReg;
pmc68681Context=(ns68681_context *) Console_Port_Data[minor].pDeviceContext;
pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
@@ -271,8 +286,10 @@ static int mc68681_negate_RTS(int minor)
* Negate RTS
*/
rtems_interrupt_disable(Irql);
pmc68681Context->ucModemCtrl&=~SP_MODEM_RTS;
(*setReg)(pMC68681, NS68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#if 0
pmc68681Context->ucModemCtrl &= ~SP_MODEM_RTS;
(*setReg)(pMC68681, MC68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#endif
rtems_interrupt_enable(Irql);
return 0;
}
@@ -281,17 +298,20 @@ static int mc68681_negate_RTS(int minor)
* These flow control routines utilise a connection from the local DTR
* line to the remote CTS line
*/
/*
* mc68681_assert_DTR
*/
static int mc68681_assert_DTR(int minor)
{
/* XXX */
unsigned32 pMC68681;
unsigned32 Irql;
mc68681_context *pns68681Context;
mc68681_context *pmc68681Context;
setRegister_f setReg;
pmc68681Context=(ns68681_context *) Console_Port_Data[minor].pDeviceContext;
pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
@@ -300,8 +320,10 @@ static int mc68681_assert_DTR(int minor)
* Assert DTR
*/
rtems_interrupt_disable(Irql);
pmc68681Context->ucModemCtrl|=SP_MODEM_DTR;
(*setReg)(pMC68681, NS68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#if 0
pmc68681Context->ucModemCtrl |= SP_MODEM_DTR;
(*setReg)(pMC68681, MC68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
#endif
rtems_interrupt_enable(Irql);
return 0;
}
@@ -309,14 +331,16 @@ static int mc68681_assert_DTR(int minor)
/*
* mc68681_negate_DTR
*/
static int mc68681_negate_DTR(int minor)
{
/* XXX */
unsigned32 pMC68681;
unsigned32 Irql;
mc68681_context *pns68681Context;
mc68681_context *pmc68681Context;
setRegister_f setReg;
pmc68681Context=(ns68681_context *) Console_Port_Data[minor].pDeviceContext;
pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
@@ -325,8 +349,10 @@ static int mc68681_negate_DTR(int minor)
* Negate DTR
*/
rtems_interrupt_disable(Irql);
pmc68681Context->ucModemCtrl&=~SP_MODEM_DTR;
(*setReg)(pMC68681, NS68681_MODEM_CONTROL,pmc68681Context->ucModemCtrl);
#if 0
pmc68681Context->ucModemCtrl &= ~SP_MODEM_DTR;
(*setReg)(pMC68681, MC68681_MODEM_CONTROL,pmc68681Context->ucModemCtrl);
#endif
rtems_interrupt_enable(Irql);
return 0;
}
@@ -334,7 +360,7 @@ static int mc68681_negate_DTR(int minor)
/*
* mc68681_isr
*
* This routine is the console interrupt handler for COM1 and COM2
* This routine is the console interrupt handler.
*
* Input parameters:
* vector - vector number
@@ -348,6 +374,7 @@ static void mc68681_process(
int minor
)
{
/* XXX */
unsigned32 pMC68681;
volatile unsigned8 ucLineStatus;
volatile unsigned8 ucInterruptId;
@@ -355,20 +382,24 @@ static void mc68681_process(
getRegister_f getReg;
setRegister_f setReg;
#if 1
cChar = ucInterruptId = ucLineStatus = 0;
#endif
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
getReg = Console_Port_Tbl[minor].getRegister;
setReg = Console_Port_Tbl[minor].setRegister;
#if 0
do {
/*
* Deal with any received characters
*/
while(TRUE) {
ucLineStatus = (*getReg)(pMC68681, NS68681_LINE_STATUS);
ucLineStatus = (*getReg)(pMC68681, MC68681_LINE_STATUS);
if(~ucLineStatus & SP_LSR_RDY) {
break;
}
cChar = (*getReg)(pMC68681, NS68681_RECEIVE_BUFFER);
cChar = (*getReg)(pMC68681, MC68681_RECEIVE_BUFFER);
rtems_termios_enqueue_raw_characters(
Console_Port_Data[minor].termios_data,
&cChar,
@@ -378,8 +409,8 @@ static void mc68681_process(
while(TRUE) {
if(Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) {
Console_Port_Data[minor].bActive=FALSE;
if(Console_Port_Tbl[minor].pDeviceFlow !=&mc68681_flow_RTSCTS) {
Console_Port_Data[minor].bActive = FALSE;
if(Console_Port_Tbl[minor].pDeviceFlow != &mc68681_flow_RTSCTS) {
mc68681_negate_RTS(minor);
}
@@ -389,7 +420,7 @@ static void mc68681_process(
break;
}
ucLineStatus = (*getReg)(pMC68681, NS68681_LINE_STATUS);
ucLineStatus = (*getReg)(pMC68681, MC68681_LINE_STATUS);
if(~ucLineStatus & SP_LSR_THOLD) {
/*
* We'll get another interrupt when
@@ -403,12 +434,13 @@ static void mc68681_process(
/*
* transmit character
*/
(*setReg)(pMC68681, NS68681_TRANSMIT_BUFFER, cChar);
(*setReg)(pMC68681, MC68681_TRANSMIT_BUFFER, cChar);
}
ucInterruptId = (*getReg)(pMC68681, NS68681_INTERRUPT_ID);
ucInterruptId = (*getReg)(pMC68681, MC68681_INTERRUPT_ID);
}
while((ucInterruptId&0xf)!=0x1);
while((ucInterruptId&0xf) != 0x1);
#endif
}
static rtems_isr mc68681_isr(
@@ -417,8 +449,8 @@ static rtems_isr mc68681_isr(
{
int minor;
for(minor=0;minor<Console_Port_Count;minor++) {
if(vector==Console_Port_Tbl[minor].ulIntVector) {
for(minor=0 ; minor<Console_Port_Count ; minor++) {
if(vector == Console_Port_Tbl[minor].ulIntVector) {
mc68681_process(minor);
}
}
@@ -427,6 +459,7 @@ static rtems_isr mc68681_isr(
/*
* mc68681_flush
*/
static int mc68681_flush(int major, int minor, void *arg)
{
while(!Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) {
@@ -460,19 +493,24 @@ static void mc68681_enable_interrupts(
int minor
)
{
/* XXX */
unsigned32 pMC68681;
unsigned8 ucDataByte;
setRegister_f setReg;
setRegister_f setReg;
#if 1
ucDataByte = 0;
#endif
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
setReg = Console_Port_Tbl[minor].setRegister;
#if 0
/*
* Enable interrupts
*/
ucDataByte = SP_INT_RX_ENABLE | SP_INT_TX_ENABLE;
(*setReg)(pMC68681, NS68681_INTERRUPT_ENABLE, ucDataByte);
(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, ucDataByte);
#endif
}
static void mc68681_initialize_interrupts(int minor)
@@ -492,8 +530,8 @@ static void mc68681_initialize_interrupts(int minor)
* mc68681_write_support_int
*
* Console Termios output entry point.
*
*/
static int mc68681_write_support_int(
int minor,
const char *buf,
@@ -503,7 +541,7 @@ static int mc68681_write_support_int(
int i;
unsigned32 Irql;
for(i=0; i<len;) {
for(i=0 ; i<len ;) {
if(Ring_buffer_Is_full(&Console_Port_Data[minor].TxBuffer)) {
if(!Console_Port_Data[minor].bActive) {
/*
@@ -537,13 +575,14 @@ static int mc68681_write_support_int(
/*
* Ensure that characters are on the way
*/
if(!Console_Port_Data[minor].bActive) {
/*
* Wake up the device
*/
rtems_interrupt_disable(Irql);
Console_Port_Data[minor].bActive = TRUE;
if(Console_Port_Tbl[minor].pDeviceFlow !=&mc68681_flow_RTSCTS) {
if(Console_Port_Tbl[minor].pDeviceFlow != &mc68681_flow_RTSCTS) {
mc68681_assert_RTS(minor);
}
mc68681_process(minor);
@@ -559,6 +598,7 @@ static int mc68681_write_support_int(
* Console Termios output entry point.
*
*/
static int mc68681_write_support_polled(
int minor,
const char *buf,
@@ -598,14 +638,16 @@ static int mc68681_inbyte_nonblocking_polled(
unsigned char ucLineStatus;
char cChar;
getRegister_f getReg;
getData_f getData;
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
getReg = Console_Port_Tbl[minor].getRegister;
getData = Console_Port_Tbl[minor].getData;
ucLineStatus = (*getReg)(pMC68681, NS68681_LINE_STATUS);
if(ucLineStatus & SP_LSR_RDY) {
cChar = (*getReg)(pMC68681, NS68681_RECEIVE_BUFFER);
return((int)cChar);
ucLineStatus = (*getReg)(pMC68681, MC68681_STATUS_REG);
if(ucLineStatus & MC68681_RX_READY) {
cChar = (*getData)(pMC68681);
return (int)cChar;
} else {
return(-1);
}

9
c/src/libchip/serial/mc68681.h
View File

@@ -18,15 +18,24 @@
extern "C" {
#endif
/*
* These are just used in the interface between this driver and
* the read/write register routines.
*/
#define MC68681_STATUS_REG 0xFF
/*
* Driver function table
*/
extern console_fns mc68681_fns;
extern console_fns mc68681_fns_polled;
/*
* Flow control function tables
*/
extern console_flow mc68681_flow_RTSCTS;
extern console_flow mc68681_flow_DTRCTS;

243
c/src/libchip/serial/mc68681_p.h
View File

@@ -18,6 +18,209 @@
extern "C" {
#endif
/*
* mc68681 register offsets Read/Write Addresses
*/
#define MC68681_MODE_REG_1A 0 /* MR1A-MR Prior to Read */
#define MC68681_MODE_REG_2A 0 /* MR2A-MR After Read */
#define MC68681_COUNT_MODE_CURRENT_MSB 6 /* CTU */
#define MC68681_COUNTER_TIMER_UPPER_REG 6 /* CTU */
#define MC68681_COUNT_MODE_CURRENT_LSB 7 /* CTL */
#define MC68681_COUNTER_TIMER_LOWER_REG 7 /* CTL */
#define MC68681_INTERRUPT_VECTOR_REG 12 /* IVR */
#define MC68681_MODE_REG_1B 8 /* MR1B-MR Prior to Read */
#define MC68681_MODE_REG_2B 8 /* MR2BA-MR After Read */
/*
* mc68681 register offsets Read Only Addresses
*/
#define MC68681_STATUS_REG_A 1 /* SRA */
#define MC68681_MASK_ISR_REG 2 /* MISR */
#define MC68681_RECEIVE_BUFFER_A 3 /* RHRA */
#define MC68681_INPUT_PORT_CHANGE_REG 4 /* IPCR */
#define MC68681_INTERRUPT_STATUS_REG 5 /* ISR */
#define MC68681_STATUS_REG_B 9 /* SRB */
#define MC68681_RECEIVE_BUFFER_B 11 /* RHRB */
#define MC68681_INPUT_PORT 13 /* IP */
#define MC68681_START_COUNT_CMD 14 /* SCC */
#define MC68681_STOP_COUNT_CMD 15 /* STC */
/*
* mc68681 register offsets Write Only Addresses
*/
#define MC68681_CLOCK_SELECT_REG_A 1 /* CSRA */
#define MC68681_COMMAND_REG_A 2 /* CRA */
#define MC68681_TRANSMIT_BUFFER_A 3 /* THRA */
#define MC68681_AUX_CTRL_REG 4 /* ACR */
#define MC68681_INTERRUPT_MASK_REG 5 /* IMR */
#define MC68681_CLOCK_SELECT_REG_B 9 /* CSRB */
#define MC68681_COMMAND_REG_B 10 /* CRB */
#define MC68681_TRANSMIT_BUFFER_B 11 /* THRB */
#define MC68681_OUTPUT_PORT_CONFIG_REG 13 /* OPCR */
#define MC68681_OUTPUT_PORT_SET_REG 14 /* SOPBC */
#define MC68681_OUTPUT_PORT_RESET_BITS 15 /* COPBC */
/*
* DUART Command Register Definitions:
*
* MC68681_COMMAND_REG_A,MC68681_COMMAND_REG_B
*/
#define MC68681_MODE_REG_ENABLE_RX 0x01
#define MC68681_MODE_REG_DISABLE_RX 0x02
#define MC68681_MODE_REG_ENABLE_TX 0x04
#define MC68681_MODE_REG_DISABLE_TX 0x08
#define MC68681_MODE_REG_RESET_MR_PTR 0x10
#define MC68681_MODE_REG_RESET_RX 0x20
#define MC68681_MODE_REG_RESET_TX 0x30
#define MC68681_MODE_REG_RESET_ERROR 0x40
#define MC68681_MODE_REG_RESET_BREAK 0x50
#define MC68681_MODE_REG_START_BREAK 0x60
#define MC68681_MODE_REG_STOP_BREAK 0x70
#define MC68681_MODE_REG_SET_RX_BRG 0x80
#define MC68681_MODE_REG_CLEAR_RX_BRG 0x90
#define MC68681_MODE_REG_SET_TX_BRG 0xa0
#define MC68681_MODE_REG_CLEAR_TX_BRG 0xb0
#define MC68681_MODE_REG_SET_STANDBY 0xc0
#define MC68681_MODE_REG_SET_ACTIVE 0xd0
/*
* Mode Register Definitions
*
* MC68681_MODE_REG_1A
* MC68681_MODE_REG_1B
*/
#define MC68681_5BIT_CHARS 0x00
#define MC68681_6BIT_CHARS 0x01
#define MC68681_7BIT_CHARS 0x02
#define MC68681_8BIT_CHARS 0x03
#define MC68681_ODD_PARITY 0x00
#define MC68681_EVEN_PARITY 0x04
#define MC68681_WITH_PARITY 0x00
#define MC68681_FORCE_PARITY 0x08
#define MC68681_NO_PARITY 0x10
#define MC68681_MULTI_DROP 0x18
#define MC68681_ERR_MODE_CHAR 0x00
#define MC68681_ERR_MODE_BLOCK 0x20
#define MC68681_RX_INTR_RX_READY 0x00
#define MC68681_RX_INTR_FFULL 0x40
#define MC68681_NO_RX_RTS_CTL 0x00
#define MC68681_RX_RTS_CTRL 0x80
/*
* Mode Register Definitions
*
* MC68681_MODE_REG_2A
* MC68681_MODE_REG_2B
*/
#define MC68681_STOP_BIT_LENGTH__563 0x00
#define MC68681_STOP_BIT_LENGTH__625 0x01
#define MC68681_STOP_BIT_LENGTH__688 0x02
#define MC68681_STOP_BIT_LENGTH__75 0x03
#define MC68681_STOP_BIT_LENGTH__813 0x04
#define MC68681_STOP_BIT_LENGTH__875 0x05
#define MC68681_STOP_BIT_LENGTH__938 0x06
#define MC68681_STOP_BIT_LENGTH_1 0x07
#define MC68681_STOP_BIT_LENGTH_1_563 0x08
#define MC68681_STOP_BIT_LENGTH_1_625 0x09
#define MC68681_STOP_BIT_LENGTH_1_688 0x0a
#define MC68681_STOP_BIT_LENGTH_1_75 0x0b
#define MC68681_STOP_BIT_LENGTH_1_813 0x0c
#define MC68681_STOP_BIT_LENGTH_1_875 0x0d
#define MC68681_STOP_BIT_LENGTH_1_938 0x0e
#define MC68681_STOP_BIT_LENGTH_2 0x0f
#define MC68681_CTS_ENABLE_TX 0x10
#define MC68681_TX_RTS_CTRL 0x20
#define MC68681_CHANNEL_MODE_NORMAL 0x00
#define MC68681_CHANNEL_MODE_ECHO 0x40
#define MC68681_CHANNEL_MODE_LOCAL_LOOP 0x80
#define MC68681_CHANNEL_MODE_REMOTE_LOOP 0xc0
/*
* Status Register Definitions
*
* MC68681_STATUS_REG_A, MC68681_STATUS_REG_B
*/
#define MC68681_RX_READY 0x01
#define MC68681_FFULL 0x02
#define MC68681_TX_READY 0x04
#define MC68681_TX_EMPTY 0x08
#define MC68681_OVERRUN_ERROR 0x10
#define MC68681_PARITY_ERROR 0x20
#define MC68681_FRAMING_ERROR 0x40
#define MC68681_RECEIVED_BREAK 0x80
/*
* Interupt Status Register Definitions.
*
* MC68681_INTERRUPT_STATUS_REG
*/
/*
* Interupt Mask Register Definitions
*
* MC68681_INTERRUPT_MASK_REG
*/
#define MC68681_IR_TX_READY_A 0x01
#define MC68681_IR_RX_READY_A 0x02
#define MC68681_IR_BREAK_A 0x04
#define MC68681_IR_COUNTER_READY 0x08
#define MC68681_IR_TX_READY_B 0x10
#define MC68681_IR_RX_READY_B 0x20
#define MC68681_IR_BREAK_B 0x40
#define MC68681_IR_INPUT_PORT_CHANGE 0x80
/*
* Status Register Definitions.
*
* MC68681_STATUS_REG_A,MC68681_STATUS_REG_B
*/
#define MC68681_STATUS_RXRDY 0x01
#define MC68681_STATUS_FFULL 0x02
#define MC68681_STATUS_TXRDY 0x04
#define MC68681_STATUS_TXEMT 0x08
#define MC68681_STATUS_OVERRUN_ERROR 0x10
#define MC68681_STATUS_PARITY_ERROR 0x20
#define MC68681_STATUS_FRAMING_ERROR 0x40
#define MC68681_STATUS_RECEIVED_BREAK 0x80
/*
* Definitions for the Interrupt Vector Register:
*
* MC68681_INTERRUPT_VECTOR_REG
*/
#define MC68681_INTERRUPT_VECTOR_INIT 0x0f
/*
* Definitions for the Auxiliary Control Register
*
* MC68681_AUX_CTRL_REG
*/
#define MC68681_AUX_BRG_SET1 0x00
#define MC68681_AUX_BRG_SET2 0x80
/*
* Per chip context control
*/
typedef struct _mc68681_context
{
@@ -32,36 +235,36 @@ static boolean mc68681_probe(int minor);
static void mc68681_init(int minor);
static int mc68681_open(
int major,
int minor,
void * arg
int major,
int minor,
void * arg
);
static int mc68681_close(
int major,
int minor,
void * arg
int major,
int minor,
void * arg
);
static void mc68681_write_polled(
int minor,
char cChar
int minor,
char cChar
);
static int mc68681_assert_RTS(
int minor
int minor
);
static int mc68681_negate_RTS(
int minor
int minor
);
static int mc68681_assert_DTR(
int minor
int minor
);
static int mc68681_negate_DTR(
int minor
int minor
);
static void mc68681_initialize_interrupts(int minor);
@@ -69,19 +272,19 @@ static void mc68681_initialize_interrupts(int minor);
static int mc68681_flush(int major, int minor, void *arg);
static int mc68681_write_support_int(
int minor,
const char *buf,
int len
int minor,
const char *buf,
int len
);
static int mc68681_write_support_polled(
int minor,
const char *buf,
int len
);
int minor,
const char *buf,
int len
);
static int mc68681_inbyte_nonblocking_polled(
int minor
int minor
);
#ifdef __cplusplus