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bsp/xilinx-zynq: New BSP

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This commit is contained in:
Sebastian Huber
2013-05-06 14:34:55 +02:00
parent 12d182c435
commit a94d46c84b
18 changed files with 1102 additions and 0 deletions
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2
c/src/lib/libbsp/arm/acinclude.m4
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@@ -34,6 +34,8 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
AC_CONFIG_SUBDIRS([smdk2410]);; AC_CONFIG_SUBDIRS([smdk2410]);;
stm32f4 ) stm32f4 )
AC_CONFIG_SUBDIRS([stm32f4]);; AC_CONFIG_SUBDIRS([stm32f4]);;
xilinx-zynq )
AC_CONFIG_SUBDIRS([xilinx-zynq]);;
*) *)
AC_MSG_ERROR([Invalid BSP]);; AC_MSG_ERROR([Invalid BSP]);;
esac esac

131
c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am Normal file
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@@ -0,0 +1,131 @@
##
#
# @file
#
# @brief Makefile of LibBSP for the Xilinx Zynq platform.
#
ACLOCAL_AMFLAGS = -I ../../../../aclocal
include $(top_srcdir)/../../../../automake/compile.am
include_bspdir = $(includedir)/bsp
include_libcpudir = $(includedir)/libcpu
dist_project_lib_DATA = bsp_specs
###############################################################################
# Header #
###############################################################################
include_HEADERS = include/bsp.h
include_HEADERS += include/tm27.h
nodist_include_HEADERS = ../../shared/include/coverhd.h \
include/bspopts.h
nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
include_bsp_HEADERS =
include_bsp_HEADERS += ../../shared/include/utility.h
include_bsp_HEADERS += ../../shared/include/irq-generic.h
include_bsp_HEADERS += ../../shared/include/irq-info.h
include_bsp_HEADERS += ../../shared/include/stackalloc.h
include_bsp_HEADERS += ../../shared/tod.h
include_bsp_HEADERS += ../shared/include/start.h
include_bsp_HEADERS += ../shared/include/arm-a9mpcore-irq.h
include_bsp_HEADERS += ../shared/include/arm-a9mpcore-regs.h
include_bsp_HEADERS += ../shared/include/arm-cp15-start.h
include_bsp_HEADERS += ../shared/include/arm-gic.h
include_bsp_HEADERS += ../shared/include/arm-gic-irq.h
include_bsp_HEADERS += ../shared/include/arm-gic-regs.h
include_bsp_HEADERS += ../shared/include/arm-gic-tm27.h
include_bsp_HEADERS += include/irq.h
include_bsp_HEADERS += include/zynq-uart.h
include_bsp_HEADERS += include/zynq-uart-regs.h
include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h
###############################################################################
# Data #
###############################################################################
noinst_LIBRARIES = libbspstart.a
libbspstart_a_SOURCES = ../shared/start/start.S
project_lib_DATA = start.$(OBJEXT)
project_lib_DATA += startup/linkcmds
EXTRA_DIST =
###############################################################################
# LibBSP #
###############################################################################
noinst_LIBRARIES += libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS =
libbsp_a_LIBADD =
# Shared
libbsp_a_SOURCES += ../../shared/bootcard.c
libbsp_a_SOURCES += ../../shared/bspclean.c
libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
libbsp_a_SOURCES += ../../shared/bsplibc.c
libbsp_a_SOURCES += ../../shared/bsppost.c
libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
libbsp_a_SOURCES += ../../shared/sbrk.c
libbsp_a_SOURCES += ../../shared/timerstub.c
libbsp_a_SOURCES += ../../shared/src/stackalloc.c
libbsp_a_SOURCES += ../shared/abort/simple_abort.c
libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S
libbsp_a_SOURCES += ../shared/arm-cp15-set-exception-handler.c
libbsp_a_SOURCES += ../shared/arm-cp15-set-ttb-entries.c
# Startup
libbsp_a_SOURCES += startup/bspreset.c
libbsp_a_SOURCES += startup/bspstart.c
# IRQ
libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c
libbsp_a_SOURCES += ../../shared/src/irq-generic.c
libbsp_a_SOURCES += ../../shared/src/irq-info.c
libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
libbsp_a_SOURCES += ../../shared/src/irq-server.c
libbsp_a_SOURCES += ../../shared/src/irq-shell.c
libbsp_a_SOURCES += ../shared/arm-gic-irq.c
# Console
libbsp_a_SOURCES += ../../shared/console.c
libbsp_a_SOURCES += ../../shared/console_control.c
libbsp_a_SOURCES += ../../shared/console_read.c
libbsp_a_SOURCES += ../../shared/console_select.c
libbsp_a_SOURCES += ../../shared/console_write.c
libbsp_a_SOURCES += console/console-config.c
libbsp_a_SOURCES += console/zynq-uart.c
# Clock
libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c
###############################################################################
# Special Rules #
###############################################################################
DISTCLEANFILES = include/bspopts.h
include $(srcdir)/preinstall.am
include $(top_srcdir)/../../../../automake/local.am

13
c/src/lib/libbsp/arm/xilinx-zynq/README Normal file
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@@ -0,0 +1,13 @@
Tested only on Qemu.
git clone git://git.qemu.org/qemu.git qemu
cd qemu
git co a1bff71c56f2d1048244c829b63797940dd4ba0e
mkdir build
cd build
../configure --prefix=/opt/qemu --interp-prefix=/opt/qemu
make
make install
export PATH="$PATH:/opt/qemu/bin"
qemu-system-arm -S -s -no-reboot -serial mon:stdio -serial /dev/null -net none -nographic -M xilinx-zynq-a9 -m 256M -kernel ticker.exe

13
c/src/lib/libbsp/arm/xilinx-zynq/bsp_specs Normal file
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@@ -0,0 +1,13 @@
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
*startfile:
%{!qrtems: %(old_startfile)} \
%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}}
*link:
%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N}
*endfile:
%{!qrtems: *(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s }

34
c/src/lib/libbsp/arm/xilinx-zynq/configure.ac Normal file
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@@ -0,0 +1,34 @@
##
#
# @file
#
# @brief Configure script of LibBSP for the Xilinx Zynq platform.
#
AC_PREREQ([2.69])
AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
AC_CONFIG_SRCDIR([bsp_specs])
RTEMS_TOP(../../../../../..)
RTEMS_CANONICAL_TARGET_CPU
AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
RTEMS_BSP_CONFIGURE
RTEMS_PROG_CC_FOR_TARGET
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
RTEMS_CHECK_NETWORKING
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U])
RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz])
RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
RTEMS_BSP_LINKCMDS
AC_CONFIG_FILES([Makefile])
AC_OUTPUT

93
c/src/lib/libbsp/arm/xilinx-zynq/console/console-config.c Normal file
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@@ -0,0 +1,93 @@
/*
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#include <libchip/serial.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/zynq-uart.h>
console_tbl Console_Configuration_Ports[] = {
{
.sDeviceName = "/dev/ttyS0",
.deviceType = SERIAL_CUSTOM,
.pDeviceFns = &zynq_uart_fns,
.deviceProbe = NULL,
.pDeviceFlow = NULL,
.ulMargin = 0,
.ulHysteresis = 0,
.pDeviceParams = (void *) 115200,
.ulCtrlPort1 = 0xe0000000,
.ulCtrlPort2 = 0,
.ulDataPort = 0,
.getRegister = NULL,
.setRegister = NULL,
.getData = NULL,
.setData = NULL,
.ulClock = 0,
.ulIntVector = ZYNQ_IRQ_UART_0
}, {
.sDeviceName = "/dev/ttyS1",
.deviceType = SERIAL_CUSTOM,
.pDeviceFns = &zynq_uart_fns,
.deviceProbe = NULL,
.pDeviceFlow = NULL,
.ulMargin = 0,
.ulHysteresis = 0,
.pDeviceParams = (void *) 115200,
.ulCtrlPort1 = 0xe0001000,
.ulCtrlPort2 = 0,
.ulDataPort = 0,
.getRegister = NULL,
.setRegister = NULL,
.getData = NULL,
.setData = NULL,
.ulClock = 0,
.ulIntVector = ZYNQ_IRQ_UART_1
}
};
unsigned long Console_Configuration_Count =
RTEMS_ARRAY_SIZE(Console_Configuration_Ports);
static void output_char(char c)
{
int minor = (int) Console_Port_Minor;
const console_tbl *ct = Console_Port_Tbl != NULL ?
Console_Port_Tbl[minor] : &Console_Configuration_Ports[minor];
const console_fns *cf = ct->pDeviceFns;
if (c == '\n') {
(*cf->deviceWritePolled)(minor, '\r');
}
(*cf->deviceWritePolled)(minor, c);
}
static void output_char_init(char c)
{
if (Console_Port_Tbl == NULL) {
int minor = (int) Console_Port_Minor;
const console_fns *cf = Console_Configuration_Ports[minor].pDeviceFns;
(*cf->deviceInitialize)(minor);
}
BSP_output_char = output_char;
output_char(c);
}
BSP_output_char_function_type BSP_output_char = output_char_init;
BSP_polling_getchar_function_type BSP_poll_char = NULL;

119
c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c Normal file
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@@ -0,0 +1,119 @@
/*
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#include <bsp/zynq-uart.h>
#include <bsp/zynq-uart-regs.h>
#include <libchip/sersupp.h>
static volatile zynq_uart *zynq_uart_get_regs(int minor)
{
const console_tbl *ct = Console_Port_Tbl != NULL ?
Console_Port_Tbl[minor] : &Console_Configuration_Ports[minor];
return (volatile zynq_uart *) ct->ulCtrlPort1;
}
static void zynq_uart_initialize(int minor)
{
volatile zynq_uart *regs = zynq_uart_get_regs(minor);
regs->control = ZYNQ_UART_CONTROL_RXDIS
| ZYNQ_UART_CONTROL_TXDIS
| ZYNQ_UART_CONTROL_RXRES
| ZYNQ_UART_CONTROL_TXRES;
regs->mode = ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL)
| ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE)
| ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(1);
regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(0xff);
regs->rx_fifo_trg_lvl = ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(0);
regs->rx_timeout = ZYNQ_UART_RX_TIMEOUT_RTO(0);
regs->control = ZYNQ_UART_CONTROL_RXEN
| ZYNQ_UART_CONTROL_TXEN
| ZYNQ_UART_CONTROL_STTBRK
| ZYNQ_UART_CONTROL_RSTTO;
}
static int zynq_uart_first_open(int major, int minor, void *arg)
{
rtems_libio_open_close_args_t *oc = (rtems_libio_open_close_args_t *) arg;
struct rtems_termios_tty *tty = (struct rtems_termios_tty *) oc->iop->data1;
console_data *cd = &Console_Port_Data[minor];
const console_tbl *ct = Console_Port_Tbl[minor];
cd->termios_data = tty;
rtems_termios_set_initial_baud(tty, (rtems_termios_baud_t) ct->pDeviceParams);
return 0;
}
static int zynq_uart_last_close(int major, int minor, void *arg)
{
return 0;
}
static int zynq_uart_read_polled(int minor)
{
volatile zynq_uart *regs = zynq_uart_get_regs(minor);
if ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_REMPTY) != 0) {
return -1;
} else {
return ZYNQ_UART_TX_RX_FIFO_FIFO_GET(regs->tx_rx_fifo);
}
}
static void zynq_uart_write_polled(int minor, char c)
{
volatile zynq_uart *regs = zynq_uart_get_regs(minor);
while ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TFUL) != 0) {
/* Wait */
}
regs->tx_rx_fifo = ZYNQ_UART_TX_RX_FIFO_FIFO(c);
}
static ssize_t zynq_uart_write_support_polled(
int minor,
const char *s,
size_t n
)
{
ssize_t i = 0;
for (i = 0; i < n; ++i) {
zynq_uart_write_polled(minor, s[i]);
}
return n;
}
static int zynq_uart_set_attribues(int minor, const struct termios *term)
{
return -1;
}
const console_fns zynq_uart_fns = {
.deviceProbe = libchip_serial_default_probe,
.deviceFirstOpen = zynq_uart_first_open,
.deviceLastClose = zynq_uart_last_close,
.deviceRead = zynq_uart_read_polled,
.deviceWrite = zynq_uart_write_support_polled,
.deviceInitialize = zynq_uart_initialize,
.deviceWritePolled = zynq_uart_write_polled,
.deviceSetAttributes = zynq_uart_set_attribues,
.deviceOutputUsesInterrupts = false
};

76
c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h Normal file
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@@ -0,0 +1,76 @@
/*
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef LIBBSP_ARM_XILINX_ZYNQ_BSP_H
#define LIBBSP_ARM_XILINX_ZYNQ_BSP_H
#include <bspopts.h>
#define BSP_FEATURE_IRQ_EXTENSION
#ifndef ASM
#include <rtems.h>
#include <rtems/console.h>
#include <rtems/clockdrv.h>
#include <bsp/default-initial-extension.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define BSP_ARM_MMU_CLIENT_DOMAIN 15U
#define BSP_ARM_MMU_READ_ONLY \
((BSP_ARM_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
| ARM_MMU_SECT_AP_0 \
| ARM_MMU_SECT_AP_2 \
| ARM_MMU_SECT_DEFAULT)
#define BSP_ARM_MMU_READ_ONLY_CACHED \
(BSP_ARM_MMU_READ_ONLY | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
#define BSP_ARM_MMU_READ_WRITE \
((BSP_ARM_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
| ARM_MMU_SECT_AP_0 \
| ARM_MMU_SECT_DEFAULT)
#define BSP_ARM_MMU_READ_WRITE_CACHED \
(BSP_ARM_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
#define BSP_ARM_MMU_READ_WRITE_DATA \
BSP_ARM_MMU_READ_WRITE_CACHED
#define BSP_ARM_MMU_READ_ONLY_DATA \
BSP_ARM_MMU_READ_ONLY_CACHED
#define BSP_ARM_MMU_CODE BSP_ARM_MMU_READ_ONLY_CACHED
#define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600
typedef enum {
BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL,
BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE
} zynq_fatal_code;
void zynq_fatal(zynq_fatal_code code) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* ASM */
#endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */

104
c/src/lib/libbsp/arm/xilinx-zynq/include/irq.h Normal file
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@@ -0,0 +1,104 @@
/*
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
#ifndef ASM
#include <rtems/irq.h>
#include <rtems/irq-extension.h>
#include <bsp/arm-a9mpcore-irq.h>
#include <bsp/arm-gic-irq.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define ZYNQ_IRQ_CPU_0 32
#define ZYNQ_IRQ_CPU_1 33
#define ZYNQ_IRQ_L2_CACHE 34
#define ZYNQ_IRQ_OCM 35
#define ZYNQ_IRQ_PMU_0 37
#define ZYNQ_IRQ_PMU_1 38
#define ZYNQ_IRQ_XADC 39
#define ZYNQ_IRQ_DVI 40
#define ZYNQ_IRQ_SWDT 41
#define ZYNQ_IRQ_TTC_0_0 42
#define ZYNQ_IRQ_TTC_1_0 43
#define ZYNQ_IRQ_TTC_2_0 44
#define ZYNQ_IRQ_DMAC_ABORT 45
#define ZYNQ_IRQ_DMAC_0 46
#define ZYNQ_IRQ_DMAC_1 47
#define ZYNQ_IRQ_DMAC_2 48
#define ZYNQ_IRQ_DMAC_3 49
#define ZYNQ_IRQ_SMC 50
#define ZYNQ_IRQ_QUAD_SPI 51
#define ZYNQ_IRQ_GPIO 52
#define ZYNQ_IRQ_USB_0 53
#define ZYNQ_IRQ_ETHERNET_0 54
#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55
#define ZYNQ_IRQ_SDIO_0 56
#define ZYNQ_IRQ_I2C_0 57
#define ZYNQ_IRQ_SPI_0 58
#define ZYNQ_IRQ_UART_0 59
#define ZYNQ_IRQ_CAN_0 60
#define ZYNQ_IRQ_FPGA_0 61
#define ZYNQ_IRQ_FPGA_1 62
#define ZYNQ_IRQ_FPGA_2 63
#define ZYNQ_IRQ_FPGA_3 64
#define ZYNQ_IRQ_FPGA_4 65
#define ZYNQ_IRQ_FPGA_5 66
#define ZYNQ_IRQ_FPGA_6 67
#define ZYNQ_IRQ_FPGA_7 68
#define ZYNQ_IRQ_TTC_0_1 69
#define ZYNQ_IRQ_TTC_1_1 70
#define ZYNQ_IRQ_TTC_2_1 71
#define ZYNQ_IRQ_DMAC_4 72
#define ZYNQ_IRQ_DMAC_5 73
#define ZYNQ_IRQ_DMAC_6 74
#define ZYNQ_IRQ_DMAC_7 75
#define ZYNQ_IRQ_USB_1 76
#define ZYNQ_IRQ_ETHERNET_1 77
#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78
#define ZYNQ_IRQ_SDIO_1 79
#define ZYNQ_IRQ_I2C_1 80
#define ZYNQ_IRQ_SPI_1 81
#define ZYNQ_IRQ_UART_1 82
#define ZYNQ_IRQ_CAN_1 83
#define ZYNQ_IRQ_FPGA_8 84
#define ZYNQ_IRQ_FPGA_9 85
#define ZYNQ_IRQ_FPGA_10 86
#define ZYNQ_IRQ_FPGA_11 87
#define ZYNQ_IRQ_FPGA_12 88
#define ZYNQ_IRQ_FPGA_13 89
#define ZYNQ_IRQ_FPGA_14 90
#define ZYNQ_IRQ_FPGA_15 91
#define ZYNQ_IRQ_PARITY 92
#define BSP_INTERRUPT_VECTOR_MIN 0
#define BSP_INTERRUPT_VECTOR_MAX 92
#define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100
#define BSP_ARM_GIC_DIST_BASE 0xf8f01000
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* ASM */
#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */

24
c/src/lib/libbsp/arm/xilinx-zynq/include/tm27.h Normal file
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@@ -0,0 +1,24 @@
/*
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef _RTEMS_TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
#include <bsp/arm-gic-tm27.h>
#endif /* __tm27_h */

133
c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-uart-regs.h Normal file
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@@ -0,0 +1,133 @@
/*
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
#define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
#include <bsp/utility.h>
typedef struct {
uint32_t control;
#define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8)
#define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7)
#define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6)
#define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5)
#define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4)
#define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3)
#define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2)
#define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1)
#define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0)
uint32_t mode;
#define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9)
#define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9)
#define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
#define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U
#define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U
#define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U
#define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U
#define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7)
#define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7)
#define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7)
#define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U
#define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U
#define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U
#define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5)
#define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5)
#define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
#define ZYNQ_UART_MODE_PAR_EVEN 0x00U
#define ZYNQ_UART_MODE_PAR_ODD 0x01U
#define ZYNQ_UART_MODE_PAR_SPACE 0x02U
#define ZYNQ_UART_MODE_PAR_MARK 0x03U
#define ZYNQ_UART_MODE_PAR_NONE 0x04U
#define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2)
#define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2)
#define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2)
#define ZYNQ_UART_MODE_CHRL_8 0x00U
#define ZYNQ_UART_MODE_CHRL_7 0x02U
#define ZYNQ_UART_MODE_CHRL_6 0x03U
#define ZYNQ_UART_MODE_CLKS BSP_BIT32(0)
uint32_t irq_en;
uint32_t irq_dis;
uint32_t irq_mask;
uint32_t irq_sts;
#define ZYNQ_UART_TOVR BSP_BIT32(12)
#define ZYNQ_UART_TNFUL BSP_BIT32(11)
#define ZYNQ_UART_TTRIG BSP_BIT32(10)
#define ZYNQ_UART_DMSI BSP_BIT32(9)
#define ZYNQ_UART_TIMEOUT BSP_BIT32(8)
#define ZYNQ_UART_PARE BSP_BIT32(7)
#define ZYNQ_UART_FRAME BSP_BIT32(6)
#define ZYNQ_UART_ROVR BSP_BIT32(5)
#define ZYNQ_UART_TFUL BSP_BIT32(4)
#define ZYNQ_UART_TEMPTY BSP_BIT32(3)
#define ZYNQ_UART_RFUL BSP_BIT32(2)
#define ZYNQ_UART_REMPTY BSP_BIT32(1)
#define ZYNQ_UART_RTRIG BSP_BIT32(0)
uint32_t baud_rate_gen;
#define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15)
#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15)
#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
uint32_t rx_timeout;
#define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7)
#define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7)
#define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
uint32_t rx_fifo_trg_lvl;
#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5)
#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
uint32_t modem_ctrl;
#define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5)
#define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1)
#define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0)
uint32_t modem_sts;
#define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8)
#define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7)
#define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6)
#define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5)
#define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4)
#define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3)
#define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2)
#define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1)
#define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0)
uint32_t channel_sts;
#define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14)
#define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13)
#define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12)
#define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11)
#define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10)
#define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4)
#define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3)
#define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2)
#define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1)
#define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0)
uint32_t tx_rx_fifo;
#define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7)
#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7)
#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
uint32_t baud_rate_div;
#define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7)
#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7)
#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
uint32_t flow_delay;
#define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5)
#define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5)
#define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
uint32_t reserved_3c[2];
uint32_t tx_fifo_trg_lvl;
#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5)
#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
} zynq_uart;
#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */

30
c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-uart.h Normal file
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/*
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_H
#define LIBBSP_ARM_XILINX_ZYNQ_UART_H
#include <libchip/serial.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
extern const console_fns zynq_uart_fns;
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_H */

7
c/src/lib/libbsp/arm/xilinx-zynq/make/custom/xilinx_zynq_a9_qemu.cfg Normal file
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@@ -0,0 +1,7 @@
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU = arm
CPU_CFLAGS = -mcpu=cortex-a9 -mthumb
CFLAGS_OPTIMIZE_V ?= -O0 -g

140
c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am Normal file
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## Automatically generated by ampolish3 - Do not edit
if AMPOLISH3
$(srcdir)/preinstall.am: Makefile.am
$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
endif
PREINSTALL_DIRS =
DISTCLEANFILES += $(PREINSTALL_DIRS)
all-local: $(TMPINSTALL_FILES)
TMPINSTALL_FILES =
CLEANFILES = $(TMPINSTALL_FILES)
all-am: $(PREINSTALL_FILES)
PREINSTALL_FILES =
CLEANFILES += $(PREINSTALL_FILES)
$(PROJECT_LIB)/$(dirstamp):
@$(MKDIR_P) $(PROJECT_LIB)
@: > $(PROJECT_LIB)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
$(PROJECT_INCLUDE)/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)
@: > $(PROJECT_INCLUDE)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
$(PROJECT_INCLUDE)/bsp/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
@: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu
@: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h
$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
$(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h
$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h
$(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h
$(PROJECT_INCLUDE)/bsp/arm-a9mpcore-irq.h: ../shared/include/arm-a9mpcore-irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-irq.h
$(PROJECT_INCLUDE)/bsp/arm-a9mpcore-regs.h: ../shared/include/arm-a9mpcore-regs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-regs.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-regs.h
$(PROJECT_INCLUDE)/bsp/arm-cp15-start.h: ../shared/include/arm-cp15-start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-cp15-start.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-cp15-start.h
$(PROJECT_INCLUDE)/bsp/arm-gic.h: ../shared/include/arm-gic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-gic.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-gic.h
$(PROJECT_INCLUDE)/bsp/arm-gic-irq.h: ../shared/include/arm-gic-irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-gic-irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-gic-irq.h
$(PROJECT_INCLUDE)/bsp/arm-gic-regs.h: ../shared/include/arm-gic-regs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-gic-regs.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-gic-regs.h
$(PROJECT_INCLUDE)/bsp/arm-gic-tm27.h: ../shared/include/arm-gic-tm27.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-gic-tm27.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-gic-tm27.h
$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
$(PROJECT_INCLUDE)/bsp/zynq-uart.h: include/zynq-uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/zynq-uart.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/zynq-uart.h
$(PROJECT_INCLUDE)/bsp/zynq-uart-regs.h: include/zynq-uart-regs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/zynq-uart-regs.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/zynq-uart-regs.h
$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds

26
c/src/lib/libbsp/arm/xilinx-zynq/startup/bspreset.c Normal file
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@@ -0,0 +1,26 @@
/*
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#include <bsp/bootcard.h>
void bsp_reset(void)
{
volatile uint32_t *slcr_unlock = (volatile uint32_t *) 0xf8000008;
volatile uint32_t *pss_rst_ctrl = (volatile uint32_t *) 0xf8000200;
while (true) {
*slcr_unlock = 0xdf0d;
*pss_rst_ctrl = 0x1;
}
}

27
c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstart.c Normal file
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@@ -0,0 +1,27 @@
/*
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#include <bsp.h>
#include <bsp/bootcard.h>
#include <bsp/irq-generic.h>
void zynq_fatal(zynq_fatal_code code)
{
rtems_fatal(RTEMS_FATAL_SOURCE_BSP_SPECIFIC, code);
}
void bsp_start(void)
{
bsp_interrupt_initialize();
}

99
c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c Normal file
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@@ -0,0 +1,99 @@
/*
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#include <bsp.h>
#include <bsp/start.h>
#include <bsp/arm-cp15-start.h>
#include <bsp/linker-symbols.h>
BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
{
/* Do nothing */
}
BSP_START_DATA_SECTION static const arm_cp15_start_section_config
zynq_mmu_config_table[] = {
{
.begin = (uint32_t) bsp_section_fast_text_begin,
.end = (uint32_t) bsp_section_fast_text_end,
.flags = BSP_ARM_MMU_CODE
}, {
.begin = (uint32_t) bsp_section_fast_data_begin,
.end = (uint32_t) bsp_section_fast_data_end,
.flags = BSP_ARM_MMU_READ_WRITE_DATA
}, {
.begin = (uint32_t) bsp_section_start_begin,
.end = (uint32_t) bsp_section_start_end,
.flags = BSP_ARM_MMU_CODE
}, {
.begin = (uint32_t) bsp_section_vector_begin,
.end = (uint32_t) bsp_section_vector_end,
.flags = BSP_ARM_MMU_READ_WRITE_CACHED
}, {
.begin = (uint32_t) bsp_section_text_begin,
.end = (uint32_t) bsp_section_text_end,
.flags = BSP_ARM_MMU_CODE
}, {
.begin = (uint32_t) bsp_section_rodata_begin,
.end = (uint32_t) bsp_section_rodata_end,
.flags = BSP_ARM_MMU_READ_ONLY_DATA
}, {
.begin = (uint32_t) bsp_section_data_begin,
.end = (uint32_t) bsp_section_data_end,
.flags = BSP_ARM_MMU_READ_WRITE_DATA
}, {
.begin = (uint32_t) bsp_section_bss_begin,
.end = (uint32_t) bsp_section_bss_end,
.flags = BSP_ARM_MMU_READ_WRITE_DATA
}, {
.begin = (uint32_t) bsp_section_work_begin,
.end = (uint32_t) bsp_section_work_end,
.flags = BSP_ARM_MMU_READ_WRITE_DATA
}, {
.begin = (uint32_t) bsp_section_stack_begin,
.end = (uint32_t) bsp_section_stack_end,
.flags = BSP_ARM_MMU_READ_WRITE_DATA
}, {
.begin = 0xe0000000U,
.end = 0xe0200000U,
.flags = BSP_ARM_MMU_READ_WRITE
}, {
.begin = 0xf8000000U,
.end = 0xf9000000U,
.flags = BSP_ARM_MMU_READ_WRITE
}
};
BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void)
{
uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
0,
ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
);
arm_cp15_start_setup_translation_table_and_enable_mmu(
ctrl,
(uint32_t *) bsp_translation_table_base,
BSP_ARM_MMU_CLIENT_DOMAIN,
&zynq_mmu_config_table[0],
RTEMS_ARRAY_SIZE(zynq_mmu_config_table)
);
}
BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
{
bsp_start_copy_sections();
setup_mmu_and_cache();
bsp_start_clear_bss();
}

31
c/src/lib/libbsp/arm/xilinx-zynq/startup/linkcmds Normal file
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@@ -0,0 +1,31 @@
MEMORY {
RAM : ORIGIN = 0x00000000, LENGTH = 256M - 16k
RAM_MMU : ORIGIN = 0x0fffc000, LENGTH = 16k
}
REGION_ALIAS ("REGION_START", RAM);
REGION_ALIAS ("REGION_VECTOR", RAM);
REGION_ALIAS ("REGION_TEXT", RAM);
REGION_ALIAS ("REGION_TEXT_LOAD", RAM);
REGION_ALIAS ("REGION_RODATA", RAM);
REGION_ALIAS ("REGION_RODATA_LOAD", RAM);
REGION_ALIAS ("REGION_DATA", RAM);
REGION_ALIAS ("REGION_DATA_LOAD", RAM);
REGION_ALIAS ("REGION_FAST_TEXT", RAM);
REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
REGION_ALIAS ("REGION_FAST_DATA", RAM);
REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
REGION_ALIAS ("REGION_BSS", RAM);
REGION_ALIAS ("REGION_WORK", RAM);
REGION_ALIAS ("REGION_STACK", RAM);
bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
bsp_vector_table_in_start_section = 1;
bsp_translation_table_base = ORIGIN (RAM_MMU);
INCLUDE linkcmds.armv4