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Patch from John S. Gwynne <jgwynne@mrcday.com> to correct minor

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problems that prevented the 19990302 snapshot from running on
the efi332.

    I'm happy to report that rtems-19990302 is running on the efi332
    board. I have enclosed a few minor patches below to the efi332 bsp. All
    patches are within that library but one. make/custom/efi332.cfg has a
    patch to select the right CPU_CFLAGS (at one time -m68332 was a
    problem... -mcpu32 or -m68332 work fine now).
This commit is contained in:
Joel Sherrill
1999-03-16 02:26:50 +00:00
parent 6d0e13c3bd
commit a902441a25
8 changed files with 153 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
c/src/lib/libbsp/m68k/efi332/console/console.c
View File

@@ -328,7 +328,7 @@ rtems_device_driver console_read(
rtems_libio_rw_args_t *rw_args;
char *buffer;
int maximum;
int count = 0;
int count;
rw_args = (rtems_libio_rw_args_t *) arg;

10
c/src/lib/libbsp/m68k/efi332/include/efi332.h
View File

@@ -43,12 +43,10 @@
/*
* This prototype really should have the noreturn attribute but
* that causes a warning since it appears that the routine does
* return.
*
* void reboot(void) __attribute__ ((noreturn));
* that causes a warning. Not sure how to fix that.
*/
void reboot(void);
/* static void reboot(void) __attribute__ ((noreturn)); */
static void reboot(void);
__inline__ static void reboot() {asm("trap #15");}
#endif /* _EFI332_H_ */

83
c/src/lib/libbsp/m68k/efi332/start/start.c
View File

@@ -10,19 +10,17 @@
m68k_isr_entry M68Kvec[256];
m68k_isr_entry vectors[256];
char * const __argv[]= {"main", ""};
char * const __env[]= {""};
void boot_card(int argc, char * const argv[]);
/*
* This prototype really should have the noreturn attribute but
* that causes a warning since it appears that the routine does
* return.
*
* void dumby_start () __attribute__ ((noreturn));
* that causes a warning. Not sure how to fix that.
*/
/* void dumby_start () __attribute__ ((noreturn)); */
void dumby_start ();
void dumby_start() {
void boot_card();
/* We need to by-pass the link instruction since the RAM chip-
select pins are not yet configured. */
@@ -36,7 +34,7 @@ void boot_card();
movel #_end, %d0;
addl " STACK_SIZE ",%d0;
movel %d0,%sp;
link %a6, #0"
movel %d0,%a6"
);
/* include in ram_init.S */
@@ -91,16 +89,34 @@ void boot_card();
*CSBAR1 = (unsigned short int)
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
*CSBAR2 = (unsigned short int)
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0x80000 */
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
*CSBAR3 = (unsigned short int)
(((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */
*CSBAR4 = (unsigned short int)
(((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0xC0000 */
*CSBAR5 = (unsigned short int)
(0xfff8 | BS_64K); /* AVEC interrupts */
#ifdef EFI332_v040b
*CSBAR6 = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
*CSBAR8 = (unsigned short int) /* PCMCIA IOCS */
(((0x0c0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xc0000 */
*CSBAR9 = (unsigned short int) /* PCMCIA MEMCS */
(((0x0D0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xd0000 */
#else /* EFI332_v040b */
*CSBAR10 = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
#endif /* EFI332_v040b */
/* Chip-Select Options Registers */
/* see section 7 of the SIM Reference Manual */
#ifdef FLASHWRITE
*CSORBT = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | WaitStates_13 | UserSupSpace );
( BothBytes | ReadWrite | SyncAS | WaitStates_2 | UserSupSpace );
#else /* FLASHWRITE */
*CSORBT = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | WaitStates_2 | UserSupSpace );
#endif /* FLASHWRITE */
*CSOR0 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
*CSOR1 = (unsigned short int)
@@ -108,31 +124,54 @@ void boot_card();
*CSOR2 = (unsigned short int)
( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR3 = (unsigned short int)
( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR4 = (unsigned short int)
( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR5 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC );
#ifdef EFI332_v040b
*CSOR6 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
*CSOR8 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
*CSOR9 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
#else /* EFI332_v040b */
*CSOR10 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
#endif /* EFI332_v040b */
/* Chip Select Pin Assignment Register 0 */
/* see section 7 of the SIM Reference Manual */
*CSPAR0 = (unsigned short int)(
SAM(DisOut,CS_5,0x3000) | /* PC2 */
SAM(DisOut,CS_4,0x0c00) | /* PC1 */
SAM(DisOut,CS_3,0x0300) | /* AVEC (internally) */
SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS */
SAM(CS16bit,CS_1,0x0030)| /* RAM LDS */
SAM(DisOut,CS_5,0x3000) | /* AVEC (internally) */
SAM(CS16bit,CS_4,0x0c00) | /* RAM UDS, bank2 */
SAM(CS16bit,CS_3,0x0300) | /* RAM LDS, bank2 */
SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS, bank1 */
SAM(CS16bit,CS_1,0x0030)| /* RAM LDS, bank1 */
SAM(CS16bit,CS_0,0x000c)| /* W/!R */
SAM(CS16bit,CSBOOT,0x0003) /* ROM DS */
SAM(CS16bit,CSBOOT,0x0003) /* ROM CS */
);
/* Chip Select Pin Assignment Register 1 */
/* see section 7 of the SIM Reference Manual */
#ifdef EFI332_v040b
*CSPAR1 = (unsigned short int)(
SAM(CS16bit,CS_10,0x300)| /* ECLK */
SAM(DisOut,CS_10,0x300)| /* ECLK */
SAM(CS16bit,CS_9,0x0c0) | /* PCMCIA MEMCS */
SAM(CS16bit,CS_8,0x030) | /* PCMCIA IOCS */
SAM(DisOut,CS_7,0x00c) | /* PC4 */
SAM(CS16bit,CS_6,0x003) /* ROM !OE */
);
#else /* EFI332_v040b */
*CSPAR1 = (unsigned short int)(
SAM(CS16bit,CS_10,0x300)| /* ROM !OE */
SAM(DisOut,CS_9,0x0c0) | /* PC6 */
SAM(DisOut,CS_8,0x030) | /* PC5 */
SAM(DisOut,CS_7,0x00c) | /* PC4 */
SAM(DisOut,CS_6,0x003) /* PC3 */
);
#endif /* EFI332_v040b */
/* Port E and F Data Register */
/* see section 9 of the SIM Reference Manual */
@@ -179,14 +218,10 @@ void boot_card();
console_init();
/*
* Execute main with arguments argv and environment env
* Execute main with arguments argc and agrv.
*/
/* main(1, __argv, __env); */
boot_card();
boot_card(1,__argv);
reboot();
}
void reboot() {asm("trap #15");}

83
c/src/lib/libbsp/m68k/efi332/start332/start332.c
View File

@@ -10,19 +10,17 @@
m68k_isr_entry M68Kvec[256];
m68k_isr_entry vectors[256];
char * const __argv[]= {"main", ""};
char * const __env[]= {""};
void boot_card(int argc, char * const argv[]);
/*
* This prototype really should have the noreturn attribute but
* that causes a warning since it appears that the routine does
* return.
*
* void dumby_start () __attribute__ ((noreturn));
* that causes a warning. Not sure how to fix that.
*/
/* void dumby_start () __attribute__ ((noreturn)); */
void dumby_start ();
void dumby_start() {
void boot_card();
/* We need to by-pass the link instruction since the RAM chip-
select pins are not yet configured. */
@@ -36,7 +34,7 @@ void boot_card();
movel #_end, %d0;
addl " STACK_SIZE ",%d0;
movel %d0,%sp;
link %a6, #0"
movel %d0,%a6"
);
/* include in ram_init.S */
@@ -91,16 +89,34 @@ void boot_card();
*CSBAR1 = (unsigned short int)
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
*CSBAR2 = (unsigned short int)
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0x80000 */
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
*CSBAR3 = (unsigned short int)
(((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */
*CSBAR4 = (unsigned short int)
(((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0xC0000 */
*CSBAR5 = (unsigned short int)
(0xfff8 | BS_64K); /* AVEC interrupts */
#ifdef EFI332_v040b
*CSBAR6 = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
*CSBAR8 = (unsigned short int) /* PCMCIA IOCS */
(((0x0c0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xc0000 */
*CSBAR9 = (unsigned short int) /* PCMCIA MEMCS */
(((0x0D0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xd0000 */
#else /* EFI332_v040b */
*CSBAR10 = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
#endif /* EFI332_v040b */
/* Chip-Select Options Registers */
/* see section 7 of the SIM Reference Manual */
#ifdef FLASHWRITE
*CSORBT = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | WaitStates_13 | UserSupSpace );
( BothBytes | ReadWrite | SyncAS | WaitStates_2 | UserSupSpace );
#else /* FLASHWRITE */
*CSORBT = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | WaitStates_2 | UserSupSpace );
#endif /* FLASHWRITE */
*CSOR0 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
*CSOR1 = (unsigned short int)
@@ -108,31 +124,54 @@ void boot_card();
*CSOR2 = (unsigned short int)
( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR3 = (unsigned short int)
( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR4 = (unsigned short int)
( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR5 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC );
#ifdef EFI332_v040b
*CSOR6 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
*CSOR8 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
*CSOR9 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
#else /* EFI332_v040b */
*CSOR10 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
#endif /* EFI332_v040b */
/* Chip Select Pin Assignment Register 0 */
/* see section 7 of the SIM Reference Manual */
*CSPAR0 = (unsigned short int)(
SAM(DisOut,CS_5,0x3000) | /* PC2 */
SAM(DisOut,CS_4,0x0c00) | /* PC1 */
SAM(DisOut,CS_3,0x0300) | /* AVEC (internally) */
SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS */
SAM(CS16bit,CS_1,0x0030)| /* RAM LDS */
SAM(DisOut,CS_5,0x3000) | /* AVEC (internally) */
SAM(CS16bit,CS_4,0x0c00) | /* RAM UDS, bank2 */
SAM(CS16bit,CS_3,0x0300) | /* RAM LDS, bank2 */
SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS, bank1 */
SAM(CS16bit,CS_1,0x0030)| /* RAM LDS, bank1 */
SAM(CS16bit,CS_0,0x000c)| /* W/!R */
SAM(CS16bit,CSBOOT,0x0003) /* ROM DS */
SAM(CS16bit,CSBOOT,0x0003) /* ROM CS */
);
/* Chip Select Pin Assignment Register 1 */
/* see section 7 of the SIM Reference Manual */
#ifdef EFI332_v040b
*CSPAR1 = (unsigned short int)(
SAM(CS16bit,CS_10,0x300)| /* ECLK */
SAM(DisOut,CS_10,0x300)| /* ECLK */
SAM(CS16bit,CS_9,0x0c0) | /* PCMCIA MEMCS */
SAM(CS16bit,CS_8,0x030) | /* PCMCIA IOCS */
SAM(DisOut,CS_7,0x00c) | /* PC4 */
SAM(CS16bit,CS_6,0x003) /* ROM !OE */
);
#else /* EFI332_v040b */
*CSPAR1 = (unsigned short int)(
SAM(CS16bit,CS_10,0x300)| /* ROM !OE */
SAM(DisOut,CS_9,0x0c0) | /* PC6 */
SAM(DisOut,CS_8,0x030) | /* PC5 */
SAM(DisOut,CS_7,0x00c) | /* PC4 */
SAM(DisOut,CS_6,0x003) /* PC3 */
);
#endif /* EFI332_v040b */
/* Port E and F Data Register */
/* see section 9 of the SIM Reference Manual */
@@ -179,14 +218,10 @@ void boot_card();
console_init();
/*
* Execute main with arguments argv and environment env
* Execute main with arguments argc and agrv.
*/
/* main(1, __argv, __env); */
boot_card();
boot_card(1,__argv);
reboot();
}
void reboot() {asm("trap #15");}

11
c/src/lib/libbsp/m68k/efi332/startup/Makefile.in
View File

@@ -19,8 +19,13 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES=
SRCS=$(C_FILES) $(H_FILES)
OBJS=$(C_O_FILES)
# Assembly source names, if any, go here -- minus the .S
S_PIECES= except_vect_332_ROM
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
@@ -52,6 +57,8 @@ ${PGM}: ${SRCS} ${OBJS}
all: ${ARCH} $(SRCS) $(PGM)
$(INSTALL_CHANGE) $(srcdir)/linkcmds ${PROJECT_RELEASE}/lib
$(INSTALL_CHANGE) $(srcdir)/linkcmds_ROM ${PROJECT_RELEASE}/lib
$(INSTALL_CHANGE) ${ARCH}/except_vect_332_ROM.o ${PROJECT_RELEASE}/lib
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile

10
c/src/lib/libbsp/m68k/efi332/startup/linkcmds
View File

@@ -32,10 +32,10 @@ __DYNAMIC = 0;
MEMORY
{
ram : ORIGIN = 0x80000, LENGTH = 256K
ram : ORIGIN = 0x80000, LENGTH = 512K
}
__end_of_ram = 0xc0000;
__end_of_ram = 0x100000;
_copy_data_from_rom = 0;
/*
@@ -48,8 +48,10 @@ SECTIONS
CREATE_OBJECT_SYMBOLS
text_start = .;
_text_start = .;
*(.text)
. = ALIGN (16);
*(.eh_fram)
. = ALIGN (16);
@@ -69,6 +71,10 @@ SECTIONS
*(.shdata)
_endtext = .;
} > ram
.gcc_exc :
{
*(.gcc_exc)
} > ram
.data :
{
data_start = .;

15
c/src/lib/libbsp/m68k/efi332/startup/linkcmds_ROM
View File

@@ -40,10 +40,10 @@ __DYNAMIC = 0;
MEMORY
{
rom : ORIGIN = 0x00000, LENGTH = 256K
ram : ORIGIN = 0x80000, LENGTH = 256K
ram : ORIGIN = 0x80000, LENGTH = 512K
}
__end_of_ram = 0xc0000;
__end_of_ram = 0x100000;
_copy_data_from_rom = 1;
/*
@@ -57,6 +57,11 @@ SECTIONS
text_start = .;
_text_start = .;
*(.text)
. = ALIGN (16);
*(.eh_fram)
. = ALIGN (16);
etext = ALIGN(0x10);
_etext = .;
__CTOR_LIST__ = .;
@@ -73,8 +78,12 @@ SECTIONS
*(.shdata)
_endtext = .;
} > rom
.data :
.gcc_exc :
AT ( ADDR(.text) + SIZEOF( .text ) )
{
*(.gcc_exc)
} > ram
.data :
{
data_start = .;
_data_start = .;

5
make/custom/efi332.cfg
View File

@@ -14,10 +14,7 @@ RTEMS_BSP_FAMILY=efi332
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
#
# XXX JRS - my gas does not grok -m68332
#CPU_CFLAGS = -m68332
CPU_CFLAGS = -m68020
CPU_CFLAGS = -mcpu32
# optimize flag: typically -0, could use -O4 or -fast, -O4 is ok for RTEMS
CFLAGS_OPTIMIZE_V=-O4 -fomit-frame-pointer