forked from Imagelibrary/rtems
bsp/motorola_powerpc: Move bspstart.c to bsps
This shared powerpc file was only used by this BSP. This patch is a part of the BSP source reorganization. Update #3285.
This commit is contained in:
Sebastian Huber
@@ -34,7 +34,7 @@ project_lib_LIBRARIES = librtemsbsp.a
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librtemsbsp_a_SOURCES =
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# startup
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librtemsbsp_a_SOURCES += ../shared/startup/bspstart.c
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librtemsbsp_a_SOURCES += ../../../../../../bsps/powerpc/motorola_powerpc/start/bspstart.c
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librtemsbsp_a_SOURCES += ../shared/startup/bspgetworkarea.c
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librtemsbsp_a_SOURCES += ../shared/showbats.c
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librtemsbsp_a_SOURCES += ../shared/startup/bsppredriverhook.c
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@@ -1,376 +0,0 @@
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/*
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* This routine does the bulk of the system initialization.
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*/
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/*
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* COPYRIGHT (c) 1989-2007.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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* Modified to support the MCP750.
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* Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
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*/
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#include <string.h>
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#include <bsp.h>
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#include <bsp/bootcard.h>
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#include <rtems/bspIo.h>
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#include <rtems/counter.h>
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#include <bsp/consoleIo.h>
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#include <libcpu/spr.h>
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#include <bsp/residual.h>
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#include <bsp/pci.h>
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#include <bsp/openpic.h>
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#include <bsp/irq.h>
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#include <libcpu/bat.h>
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#include <libcpu/pte121.h>
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#include <libcpu/cpuIdent.h>
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#include <bsp/vectors.h>
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#include <bsp/motorola.h>
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#include <rtems/powerpc/powerpc.h>
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extern void _return_to_ppcbug(void);
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extern unsigned long __rtems_end[];
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extern void L1_caches_enables(void);
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extern unsigned get_L2CR(void);
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extern void set_L2CR(unsigned);
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extern Triv121PgTbl BSP_pgtbl_setup(unsigned int *);
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extern void BSP_pgtbl_activate(Triv121PgTbl);
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SPR_RW(SPRG1)
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#if defined(DEBUG_BATS)
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extern void ShowBATS(void);
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#endif
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/*
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* Driver configuration parameters
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*/
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uint32_t bsp_clicks_per_usec;
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/*
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* Copy of residuals passed by firmware
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*/
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RESIDUAL residualCopy;
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/*
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* Copy Additional boot param passed by boot loader
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*/
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#define MAX_LOADER_ADD_PARM 80
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char loaderParam[MAX_LOADER_ADD_PARM];
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char *BSP_commandline_string = loaderParam;
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/*
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* Vital Board data Start using DATA RESIDUAL
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*/
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/*
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* Total memory using RESIDUAL DATA
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*/
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unsigned int BSP_mem_size;
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/*
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* PCI Bus Frequency
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*/
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unsigned int BSP_bus_frequency;
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/*
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* processor clock frequency
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*/
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unsigned int BSP_processor_frequency;
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/*
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* Time base divisior (how many tick for 1 second).
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*/
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unsigned int BSP_time_base_divisor;
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/*
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* Use the shared implementations of the following routines
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*/
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char *save_boot_params(
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void *r3,
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void *r4,
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void *r5,
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char *cmdline_start,
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char *cmdline_end
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)
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{
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residualCopy = *(RESIDUAL *)r3;
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strncpy(loaderParam, cmdline_start, MAX_LOADER_ADD_PARM);
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loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
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return loaderParam;
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}
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#if defined(mvme2100)
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unsigned int EUMBBAR;
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/*
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* Return the current value of the Embedded Utilities Memory Block Base Address
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* Register (EUMBBAR) as read from the processor configuration register using
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* Processor Address Map B (CHRP).
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*/
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static unsigned int get_eumbbar(void) {
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out_le32( (volatile uint32_t *)0xfec00000, 0x80000078 );
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return in_le32( (volatile uint32_t *)0xfee00000 );
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}
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#endif
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/*
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* bsp_start
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*
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* This routine does the bulk of the system initialization.
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*/
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void bsp_start( void )
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{
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#if !defined(mvme2100)
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unsigned l2cr;
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#endif
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uintptr_t intrStackStart;
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uintptr_t intrStackSize;
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prep_t boardManufacturer;
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motorolaBoard myBoard;
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Triv121PgTbl pt=0;
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/*
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* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
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* function store the result in global variables so that it can be used
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* later...
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*/
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get_ppc_cpu_type();
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get_ppc_cpu_revision();
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/*
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* Init MMU block address translation to enable hardware access
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*/
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#if !defined(mvme2100)
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/*
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* PC legacy IO space used for inb/outb and all PC compatible hardware
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*/
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setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
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#endif
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/*
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* PCI devices memory area. Needed to access OpenPIC features
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* provided by the Raven
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*
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* T. Straumann: give more PCI address space
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*/
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setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE);
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/*
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* Must have acces to open pic PCI ACK registers provided by the RAVEN
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*/
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#ifndef qemu
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setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
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#else
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setdbat(3, 0xb0000000, 0xb0000000, 0x10000000, IO_PAGE);
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#endif
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#if defined(mvme2100)
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/* Need 0xfec00000 mapped for this */
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EUMBBAR = get_eumbbar();
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#endif
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/*
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* enables L1 Cache. Note that the L1_caches_enables() codes checks for
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* relevant CPU type so that the reason why there is no use of myCpu...
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*/
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L1_caches_enables();
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select_console(CONSOLE_LOG);
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/*
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* We check that the keyboard is present and immediately
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* select the serial console if not.
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*/
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#if defined(BSP_KBD_IOBASE)
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{ int err;
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err = kbdreset();
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if (err) select_console(CONSOLE_SERIAL);
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}
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#else
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select_console(CONSOLE_SERIAL);
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#endif
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#if !defined(mvme2100)
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/*
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* Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
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* relevant CPU type (mpc750)...
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*/
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l2cr = get_L2CR();
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#ifdef SHOW_LCR2_REGISTER
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printk("Initial L2CR value = %x\n", l2cr);
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#endif
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if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
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set_L2CR(0xb9A14000);
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#endif
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/*
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* Initialize the interrupt related settings.
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*/
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intrStackStart = (uintptr_t) __rtems_end;
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intrStackSize = rtems_configuration_get_interrupt_stack_size();
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/*
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* Initialize default raw exception handlers.
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*/
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ppc_exc_initialize(intrStackStart, intrStackSize);
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boardManufacturer = checkPrepBoardType(&residualCopy);
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if (boardManufacturer != PREP_Motorola) {
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printk("Unsupported hardware vendor\n");
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while (1);
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}
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myBoard = getMotorolaBoard();
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printk("-----------------------------------------\n");
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printk("Welcome to %s on %s\n", _RTEMS_version,
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motorolaBoardToString(myBoard));
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printk("-----------------------------------------\n");
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#ifdef SHOW_MORE_INIT_SETTINGS
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printk("Residuals are located at %x\n", (unsigned) &residualCopy);
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printk("Additionnal boot options are %s\n", loaderParam);
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printk("Software IRQ stack starts at %x with size %u\n", intrStackStart, intrStackSize);
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printk("-----------------------------------------\n");
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#endif
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#ifdef TEST_RETURN_TO_PPCBUG
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printk("Hit <Enter> to return to PPCBUG monitor\n");
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printk("When Finished hit GO. It should print <Back from monitor>\n");
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debug_getc();
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_return_to_ppcbug();
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printk("Back from monitor\n");
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_return_to_ppcbug();
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#endif /* TEST_RETURN_TO_PPCBUG */
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#ifdef SHOW_MORE_INIT_SETTINGS
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printk("Going to start PCI buses scanning and initialization\n");
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#endif
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pci_initialize();
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{
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const struct _int_map *bspmap = motorolaIntMap(currentBoard);
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if( bspmap ) {
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printk("pci : Configuring interrupt routing for '%s'\n",
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motorolaBoardToString(currentBoard));
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FixupPCI(bspmap, motorolaIntSwizzle(currentBoard));
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}
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else
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printk("pci : Interrupt routing not available for this bsp\n");
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}
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#ifdef SHOW_MORE_INIT_SETTINGS
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printk("Number of PCI buses found is : %d\n", pci_bus_count());
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#endif
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#ifdef TEST_RAW_EXCEPTION_CODE
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printk("Testing exception handling Part 1\n");
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/*
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* Cause a software exception
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*/
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__asm__ __volatile ("sc");
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/*
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* Check we can still catch exceptions and return coorectly.
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*/
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printk("Testing exception handling Part 2\n");
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__asm__ __volatile ("sc");
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/*
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* Somehow doing the above seems to clobber SPRG0 on the mvme2100. The
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* interrupt disable mask is stored in SPRG0. Is this a problem?
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*/
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ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT);
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#endif
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/* See above */
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BSP_mem_size = residualCopy.TotalMemory;
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BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz;
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BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
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BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor?
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residualCopy.VitalProductData.TimeBaseDivisor : 4000);
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/* clear hostbridge errors but leave MCP disabled -
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* PCI config space scanning code will trip otherwise :-(
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*/
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_BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);
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if (BSP_mem_size > 0x10000000)
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{
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/* Support cases of system memory size larger than 256Mb.
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*
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* We use BAT3 in order to obtain access to the top section of the RAM.
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* We also need to do this just before setting up the page table because
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* this is where the page table will be located.
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*/
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const unsigned int mem256Count = (BSP_mem_size / 0x10000000);
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const unsigned int BAT3Addr = ((BSP_mem_size % 0x10000000) ?
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(mem256Count * 0x10000000) :
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((mem256Count-1) * 0x10000000));
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setdbat(3, BAT3Addr, BAT3Addr, 0x10000000, IO_PAGE);
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#ifdef SHOW_MORE_INIT_SETTINGS
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printk("Setting up BAT3 for large memory support. (BAT3 --> 0x%x)\n", BAT3Addr);
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#endif
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}
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/* Allocate and set up the page table mappings
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* This is only available on >604 CPUs.
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*
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* NOTE: This setup routine may modify the available memory
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* size. It is essential to call it before
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* calculating the workspace etc.
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*/
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pt = BSP_pgtbl_setup(&BSP_mem_size);
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if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
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pt, TRIV121_121_VSID,
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#ifndef qemu
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0xfeff0000,
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#else
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0xbffff000,
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#endif
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1,
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TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
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printk("WARNING: unable to setup page tables VME "
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"bridge must share PCI space\n");
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}
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/*
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* initialize the device driver parameters
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*/
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bsp_clicks_per_usec = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
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rtems_counter_initialize_converter(
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BSP_bus_frequency / (BSP_time_base_divisor / 1000)
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);
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/*
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* Initalize RTEMS IRQ system
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*/
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BSP_rtems_irq_mng_init(0);
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/* Activate the page table mappings only after
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* initializing interrupts because the irq_mng_init()
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* routine needs to modify the text
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*/
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if (pt) {
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#ifdef SHOW_MORE_INIT_SETTINGS
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printk("Page table setup finished; will activate it NOW...\n");
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#endif
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BSP_pgtbl_activate(pt);
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/* finally, switch off DBAT3 */
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setdbat(3, 0, 0, 0, 0);
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}
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#if defined(DEBUG_BATS)
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ShowBATS();
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#endif
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#ifdef SHOW_MORE_INIT_SETTINGS
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printk("Exit from bspstart\n");
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#endif
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}
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