forked from Imagelibrary/rtems
Support for MPC5643L.
Rework of the start sequence to reduce the amount assembler code and to support configuration tables which may be provided by the application.
This commit is contained in:
Sebastian Huber
@@ -418,13 +418,13 @@ include_mpc55xx_HEADERS += mpc55xx/include/dspi.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/edma.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/emios.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/mpc55xx.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/esci.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/siu.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/irq.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/watchdog.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc551x.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc555x.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc556x.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc564xL.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc567x.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/regs-edma.h
|
||||
include_mpc55xx_HEADERS += mpc55xx/include/regs-mmu.h
|
||||
@@ -462,11 +462,6 @@ noinst_PROGRAMS += mpc55xx/siu.rel
|
||||
mpc55xx_siu_rel_SOURCES = mpc55xx/siu/siu.c
|
||||
mpc55xx_siu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
|
||||
|
||||
# eSCI
|
||||
noinst_PROGRAMS += mpc55xx/esci.rel
|
||||
mpc55xx_esci_rel_SOURCES = mpc55xx/esci/esci.c
|
||||
mpc55xx_esci_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
|
||||
|
||||
# DSPI
|
||||
noinst_PROGRAMS += mpc55xx/dspi.rel
|
||||
mpc55xx_dspi_rel_SOURCES = mpc55xx/dspi/dspi.c
|
||||
@@ -475,8 +470,6 @@ mpc55xx_dspi_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
|
||||
# Misc
|
||||
noinst_PROGRAMS += mpc55xx/misc.rel
|
||||
mpc55xx_misc_rel_SOURCES = mpc55xx/misc/copy.S \
|
||||
mpc55xx/misc/fmpll.S \
|
||||
mpc55xx/misc/flash.S \
|
||||
mpc55xx/misc/flash_support.c
|
||||
mpc55xx_misc_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
|
||||
|
||||
|
||||
@@ -747,6 +747,7 @@ mpc55xx_dspi_bus_entry mpc55xx_dspi_bus_table [MPC55XX_DSPI_NUMBER] = {
|
||||
},
|
||||
.idle_char = 0xffffffff,
|
||||
.baud = 0
|
||||
#ifdef DSPI_D
|
||||
}, {
|
||||
/* DSPI D */
|
||||
.bus = {
|
||||
@@ -775,5 +776,6 @@ mpc55xx_dspi_bus_entry mpc55xx_dspi_bus_table [MPC55XX_DSPI_NUMBER] = {
|
||||
},
|
||||
.idle_char = 0xffffffff,
|
||||
.baud = 0
|
||||
#endif
|
||||
}
|
||||
};
|
||||
|
||||
@@ -7,15 +7,17 @@
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008
|
||||
* Embedded Brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* D-82178 Puchheim
|
||||
* Germany
|
||||
* rtems@embedded-brains.de
|
||||
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* The license and distribution terms for this file may be found in the file
|
||||
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
|
||||
* embedded brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <mpc55xx/regs.h>
|
||||
@@ -29,6 +31,8 @@
|
||||
|
||||
#if MPC55XX_CHIP_TYPE / 10 == 551
|
||||
#define EDMA_CHANNEL_COUNT 16U
|
||||
#elif MPC55XX_CHIP_TYPE / 10 == 564
|
||||
#define EDMA_CHANNEL_COUNT 16U
|
||||
#elif MPC55XX_CHIP_TYPE / 10 == 567
|
||||
#define EDMA_CHANNEL_COUNT 96U
|
||||
#else
|
||||
|
||||
@@ -7,28 +7,22 @@
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009
|
||||
* embedded brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* D-82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
* Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <mpc55xx/regs.h>
|
||||
#include <mpc55xx/emios.h>
|
||||
#include <mpc55xx/mpc55xx.h>
|
||||
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp/utility.h>
|
||||
|
||||
#define RTEMS_STATUS_CHECKS_USE_PRINTK
|
||||
|
||||
#include <rtems/status-checks.h>
|
||||
#ifdef MPC55XX_HAS_EMIOS
|
||||
|
||||
/**
|
||||
* @brief Initialize the eMIOS module.
|
||||
@@ -107,3 +101,5 @@ void mpc55xx_emios_set_global_prescaler( unsigned prescaler)
|
||||
/* Set MCR */
|
||||
EMIOS.MCR.R = mcr.R;
|
||||
}
|
||||
|
||||
#endif /* MPC55XX_HAS_EMIOS */
|
||||
|
||||
@@ -7,12 +7,13 @@
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009
|
||||
* embedded brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* D-82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
* Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
@@ -22,18 +23,14 @@
|
||||
#ifndef LIBCPU_POWERPC_MPC55XX_EMIOS_H
|
||||
#define LIBCPU_POWERPC_MPC55XX_EMIOS_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <rtems.h>
|
||||
#include <rtems/chain.h>
|
||||
|
||||
#include <bspopts.h>
|
||||
#include <mpc55xx/regs.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifdef MPC55XX_HAS_EMIOS
|
||||
|
||||
/**
|
||||
* @name eMIOS - Modes
|
||||
*
|
||||
@@ -191,6 +188,8 @@ unsigned mpc55xx_emios_global_prescaler( void);
|
||||
|
||||
void mpc55xx_emios_set_global_prescaler( unsigned prescaler);
|
||||
|
||||
#endif /* MPC55XX_HAS_EMIOS */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
@@ -52,6 +52,8 @@
|
||||
#ifndef _MPC5510_H_
|
||||
#define _MPC5510_H_
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <mpc55xx/regs-edma.h>
|
||||
@@ -3969,6 +3971,7 @@ extern "C" {
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* ASM */
|
||||
#endif /* ifdef _MPC5510_H */
|
||||
/*********************************************************************
|
||||
*
|
||||
|
||||
@@ -103,6 +103,8 @@
|
||||
#ifndef _MPC5554_H_
|
||||
#define _MPC5554_H_
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <mpc55xx/regs-edma.h>
|
||||
@@ -3347,6 +3349,7 @@ union EQADC_WRITE_CONFIGURATION_COMMAND_tag {
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* ASM */
|
||||
#endif /* ifdef _MPC5554_H */
|
||||
/*********************************************************************
|
||||
*
|
||||
|
||||
@@ -70,6 +70,8 @@
|
||||
#ifndef _MPC5567_H_
|
||||
#define _MPC5567_H_
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <mpc55xx/regs-edma.h>
|
||||
@@ -4527,6 +4529,7 @@ extern "C" {
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* ASM */
|
||||
#endif /* ifdef _MPC5567_H */
|
||||
/*********************************************************************
|
||||
*
|
||||
|
||||
20666
c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc564xL.h
Normal file
20666
c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc564xL.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -60,6 +60,8 @@
|
||||
#ifndef _MPC5674F_H_
|
||||
#define _MPC5674F_H_
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <mpc55xx/regs-edma.h>
|
||||
@@ -6592,6 +6594,7 @@ extern "C" {
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* ASM */
|
||||
#endif /* ifdef _MPC5674_H */
|
||||
/*********************************************************************
|
||||
*
|
||||
|
||||
@@ -7,15 +7,17 @@
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008, 2010
|
||||
* Embedded Brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* D-82178 Puchheim
|
||||
* Germany
|
||||
* rtems@embedded-brains.de
|
||||
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* The license and distribution terms for this file may be found in the file
|
||||
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
|
||||
* embedded brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_POWERPC_IRQ_H
|
||||
@@ -109,6 +111,105 @@ extern "C" {
|
||||
/* FlexRay */
|
||||
#define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
|
||||
((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID)
|
||||
#elif MPC55XX_CHIP_TYPE / 10 == 564
|
||||
#define MPC55XX_IRQ_MAX 255U
|
||||
|
||||
/* eDMA */
|
||||
#define MPC55XX_IRQ_EDMA_ERROR(group) \
|
||||
((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
|
||||
#define MPC55XX_IRQ_EDMA(ch) \
|
||||
((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
|
||||
|
||||
/* SWT */
|
||||
#define MPC55XX_IRQ_SWT_0 28U
|
||||
#define MPC55XX_IRQ_SWT_1 29U
|
||||
|
||||
/* STM */
|
||||
#define MPC55XX_IRQ_STM_CHANNEL(ch) ((ch) + 30U)
|
||||
|
||||
/* ECSM */
|
||||
#define MPC55XX_IRQ_ECSM_FAS 9U
|
||||
#define MPC55XX_IRQ_ECSM_NCE 35U
|
||||
#define MPC55XX_IRQ_ECSM_COR 36U
|
||||
|
||||
/* MC */
|
||||
#define MPC55XX_IRQ_MC_ME_SAFE_MODE 51U
|
||||
#define MPC55XX_IRQ_MC_ME_MODE_TRANSITION 52U
|
||||
#define MPC55XX_IRQ_MC_ME_INVALID_MODE 53U
|
||||
#define MPC55XX_IRQ_MC_ME_INVALID_CONFIG 54U
|
||||
#define MPC55XX_IRQ_MC_RGM_FRAE 56U
|
||||
|
||||
/* XOSC */
|
||||
#define MPC55XX_IRQ_XOSC 57U
|
||||
|
||||
/* PIT */
|
||||
#define MPC55XX_IRQ_PIT_CHANNEL(ch) \
|
||||
((ch) == 3 ? 127U : ((ch) + 59U))
|
||||
|
||||
/* SIU external interrupts */
|
||||
#define MPC55XX_IRQ_SIU_EXTERNAL_0 41U
|
||||
#define MPC55XX_IRQ_SIU_EXTERNAL_1 42U
|
||||
#define MPC55XX_IRQ_SIU_EXTERNAL_2 43U
|
||||
#define MPC55XX_IRQ_SIU_EXTERNAL_3 44U
|
||||
|
||||
/* ADC */
|
||||
#define MPC55XX_IRQ_ADC_BASE(mod) \
|
||||
((mod) == 0 ? 62U : \
|
||||
((mod) == 1 ? 82U : MPC55XX_IRQ_INVALID))
|
||||
|
||||
/* DSPI */
|
||||
#define MPC55XX_IRQ_DSPI_BASE(mod) \
|
||||
((mod) == 0 ? 74U : \
|
||||
((mod) == 1 ? 94U : \
|
||||
((mod) == 2 ? 114U : MPC55XX_IRQ_INVALID)))
|
||||
|
||||
/* FlexCAN */
|
||||
#define MPC55XX_IRQ_CAN_BASE(mod) \
|
||||
((mod) == 0 ? 65U : \
|
||||
((mod) == 1 ? 85U : MPC55XX_IRQ_INVALID))
|
||||
|
||||
/* FlexPWM */
|
||||
#define MPC55XX_IRQ_FLEXPWM_BASE(mod) \
|
||||
((mod) == 0 ? 179U : \
|
||||
((mod) == 1 ? 233U : MPC55XX_IRQ_INVALID))
|
||||
|
||||
/* FlexRay */
|
||||
#define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
|
||||
((mod) == 0 ? 131U : MPC55XX_IRQ_INVALID)
|
||||
|
||||
/* LINFlexD */
|
||||
#define MPC55XX_IRQ_LINFLEX_BASE(mod) \
|
||||
((mod) == 0 ? 79U : \
|
||||
((mod) == 1 ? 99U : MPC55XX_IRQ_INVALID))
|
||||
|
||||
/* eTimer */
|
||||
#define MPC55XX_IRQ_ETIMER_BASE(mod) \
|
||||
((mod) == 0 ? 157U : \
|
||||
((mod) == 1 ? 168U : \
|
||||
((mod) == 2 ? 222U : MPC55XX_IRQ_INVALID)))
|
||||
|
||||
/* CTU */
|
||||
#define MPC55XX_IRQ_CTU_MRS 193U
|
||||
#define MPC55XX_IRQ_CTU_T(idx) ((idx) + 194U)
|
||||
#define MPC55XX_IRQ_CTU_FIFO(idx) ((idx) + 202U)
|
||||
#define MPC55XX_IRQ_CTU_ADC 206U
|
||||
#define MPC55XX_IRQ_CTU_ERR 207U
|
||||
|
||||
/* SEMA */
|
||||
#define MPC55XX_IRQ_SEMA_0 247U
|
||||
#define MPC55XX_IRQ_SEMA_1 248U
|
||||
|
||||
/* FCCU */
|
||||
#define MPC55XX_IRQ_FCCU_ALRM 250U
|
||||
#define MPC55XX_IRQ_FCCU_CFG_TO 251U
|
||||
#define MPC55XX_IRQ_FCCU_SC_RCC0_F 252U
|
||||
#define MPC55XX_IRQ_FCCU_SC_RCC1_F 253U
|
||||
|
||||
/* PMU */
|
||||
#define MPC55XX_IRQ_PMU 254U
|
||||
|
||||
/* SWG */
|
||||
#define MPC55XX_IRQ_SWG 255U
|
||||
#else
|
||||
#if MPC55XX_CHIP_TYPE / 10 == 555
|
||||
#define MPC55XX_IRQ_MAX 307U
|
||||
@@ -188,6 +289,22 @@ extern "C" {
|
||||
|
||||
#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
|
||||
|
||||
/* ADC */
|
||||
#define MPC55XX_IRQ_ADC_EOC(mod) \
|
||||
(MPC55XX_IRQ_ADC_BASE(mod) + 0U)
|
||||
#define MPC55XX_IRQ_ADC_ER(mod) \
|
||||
(MPC55XX_IRQ_ADC_BASE(mod) + 1U)
|
||||
#define MPC55XX_IRQ_ADC_WD(mod) \
|
||||
(MPC55XX_IRQ_ADC_BASE(mod) + 2U)
|
||||
|
||||
/* eTimer */
|
||||
#define MPC55XX_IRQ_ETIMER_TC(mod, ch) \
|
||||
(MPC55XX_IRQ_ETIMER_BASE(mod) + (ch))
|
||||
#define MPC55XX_IRQ_ETIMER_WTIF(mod) \
|
||||
(MPC55XX_IRQ_ETIMER_BASE(mod) + 8U)
|
||||
#define MPC55XX_IRQ_ETIMER_RCF(mod) \
|
||||
(MPC55XX_IRQ_ETIMER_BASE(mod) + 10U)
|
||||
|
||||
/* eTPU */
|
||||
#define MPC55XX_IRQ_ETPU(mod) \
|
||||
(MPC55XX_IRQ_ETPU_BASE(mod) + 0U)
|
||||
@@ -219,36 +336,71 @@ extern "C" {
|
||||
#define MPC55XX_IRQ_ESCI(mod) (MPC55XX_IRQ_ESCI_BASE(mod) + 0U)
|
||||
|
||||
/* FlexCAN */
|
||||
#define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
|
||||
#define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U)
|
||||
#if MPC55XX_CHIP_TYPE / 10 == 564
|
||||
#define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
|
||||
#define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_0_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_4_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_8_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_12_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
|
||||
#else
|
||||
#define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
|
||||
#define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U)
|
||||
#define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U)
|
||||
#endif
|
||||
|
||||
/* FlexPWM */
|
||||
#define MPC55XX_IRQ_FLEXPWM_RF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 0U)
|
||||
#define MPC55XX_IRQ_FLEXPWM_COF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 1U)
|
||||
#define MPC55XX_IRQ_FLEXPWM_CAF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 2U)
|
||||
#define MPC55XX_IRQ_FLEXPWM_FFLAG(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 12U)
|
||||
#define MPC55XX_IRQ_FLEXPWM_REF(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 13U)
|
||||
|
||||
/* FlexRay */
|
||||
#define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
|
||||
#if MPC55XX_CHIP_TYPE / 10 == 564
|
||||
#define MPC55XX_IRQ_FLEXRAY_LRNEIF_DRNEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_LRCEIF_DRCEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_FAFAIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_FAFVIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_WUPIEF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 8U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 9U)
|
||||
#else
|
||||
#define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
|
||||
#define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
|
||||
#endif
|
||||
|
||||
/* LINFlexD */
|
||||
#define MPC55XX_IRQ_LINFLEX_RXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 0U)
|
||||
#define MPC55XX_IRQ_LINFLEX_TXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 1U)
|
||||
#define MPC55XX_IRQ_LINFLEX_ERR(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 2U)
|
||||
|
||||
/* Checks */
|
||||
#define MPC55XX_IRQ_IS_VALID(v) \
|
||||
|
||||
@@ -47,12 +47,6 @@
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* Defined in fmpll.S */
|
||||
int mpc55xx_get_system_clock(void);
|
||||
|
||||
/* Defined in fmpll.S */
|
||||
void mpc55xx_system_reset(void);
|
||||
|
||||
int mpc55xx_flash_copy(void *dest, const void *src, size_t nbytes);
|
||||
int mpc55xx_flash_copy_op(void *rdest, const void *src, size_t nbytes,
|
||||
uint32_t opmask, uint32_t *p_fail_addr);
|
||||
|
||||
@@ -26,132 +26,12 @@
|
||||
#define LIBCPU_POWERPC_MPC55XX_REG_DEFS_H
|
||||
|
||||
#include <bspopts.h>
|
||||
/*
|
||||
* Register addresses
|
||||
*/
|
||||
#if ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))
|
||||
|
||||
#define FMPLL_SYNSR 0xFFFF0004
|
||||
#define FMPLL_ESYNCR1 0xFFFF0008
|
||||
#define FMPLL_ESYNCR2 0xFFFF000C
|
||||
#define FLASH_BIUCR 0xFFFF801C
|
||||
#define SIU_ECCR 0xFFFE8984
|
||||
#define SIU_SYSCLK 0xFFFE89A0
|
||||
#define SIU_SRCR 0xFFFE8010
|
||||
|
||||
/*
|
||||
* Definitions for SIU_SYSCLK
|
||||
*/
|
||||
#define SIU_SYSCLK_SYSCLKSEL_MASK 0xC0000000
|
||||
#define SIU_SYSCLK_SYSCLKSEL_IRC 0x00000000
|
||||
#define SIU_SYSCLK_SYSCLKSEL_XOSC 0x40000000
|
||||
#define SIU_SYSCLK_SYSCLKSEL_PLL 0x80000000
|
||||
|
||||
#else /* ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))*/
|
||||
|
||||
#define FMPLL_SYNCR 0xC3F80000
|
||||
#define FMPLL_SYNSR 0xC3F80004
|
||||
#define FMPLL_ESYNCR1 0XC3F80008
|
||||
#define FMPLL_ESYNCR2 0XC3F8000C
|
||||
#define FLASH_BIUCR 0xC3F8801C
|
||||
#define SIU_ECCR 0xC3F90984
|
||||
#define SIU_SRCR 0xC3F90010
|
||||
#define SIU_SYSDIV 0xC3F909A0
|
||||
|
||||
#endif /*((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))*/
|
||||
/*
|
||||
* Special purpose registers
|
||||
*/
|
||||
|
||||
#define BUCSR 1013
|
||||
|
||||
/*
|
||||
* Branch Unit Control and Status Register (BUCSR)
|
||||
*/
|
||||
|
||||
#define BUCSR_BBFI 0x00000200
|
||||
#define BUCSR_BPEN 0x00000001
|
||||
|
||||
/*
|
||||
* Definitions for FMPLL_SYNCR (FMPLL Synthesizer Control Register)
|
||||
*/
|
||||
|
||||
/* Fields used for PREDIV (Pre-Divider bits [1:3]) */
|
||||
#define FMPLL_SYNCR_PREDIV_0 0x00000000
|
||||
|
||||
/* Fields used for MFD (Muliplication Factor Divider bits [4:8]) */
|
||||
#define FMPLL_SYNCR_MFD_0 0x00000000
|
||||
#define FMPLL_SYNCR_MFD_2 0x01000000
|
||||
#define FMPLL_SYNCR_MFD_4 0x02000000
|
||||
#define FMPLL_SYNCR_MFD_6 0x03000000
|
||||
#define FMPLL_SYNCR_MFD_8 0x04000000
|
||||
#define FMPLL_SYNCR_MFD_10 0x05000000
|
||||
#define FMPLL_SYNCR_MFD_12 0x06000000
|
||||
|
||||
/* Fields used for RFD (Reduced Frequency Divider bits [10:12]) */
|
||||
#define FMPLL_SYNCR_RFD_0 0x00000000
|
||||
#define FMPLL_SYNCR_RFD_1 0x00080000
|
||||
#define FMPLL_SYNCR_RFD_2 0x00100000
|
||||
#define FMPLL_SYNCR_RFD_3 0x00180000
|
||||
#define FMPLL_SYNCR_RFD_4 0x00200000
|
||||
#define FMPLL_SYNCR_RFD_5 0x00280000
|
||||
#define FMPLL_SYNCR_RFD_6 0x00300000
|
||||
#define FMPLL_SYNCR_RFD_7 0x00380000
|
||||
|
||||
/* Fields for LOCEN (Loss-of-clock enable bit [13]) */
|
||||
#define FMPLL_SYNCR_LOCEN 0x00040000
|
||||
|
||||
/* Fields for LOLRE (Loss-of-lock reset enable bit [14]) */
|
||||
#define FMPLL_SYNCR_LOLRE 0x00020000
|
||||
|
||||
/* Fields for LOCRE (Loss-of-clock reset enable bit [15]) */
|
||||
#define FMPLL_SYNCR_LOCRE 0x00010000
|
||||
|
||||
/* Fields for DISCLK (Disable CLKOUT bit [16]) */
|
||||
#define FMPLL_SYNCR_DISCLK 0x00008000
|
||||
|
||||
/* Fields for LOLIRQ (Loss-of-lock interrupt request bit [17]) */
|
||||
#define FMPLL_SYNCR_LOLIRQ 0x00004000
|
||||
|
||||
/* Fields for LOCIRQ (Loss-of-clock interrupt request bit [18]) */
|
||||
#define FMPLL_SYNCR_LOCIRQ 0x00002000
|
||||
|
||||
/* Fields for RATE (Modulation rate bit [19]) */
|
||||
#define FMPLL_SYNCR_RATE_FREF 0x00001000
|
||||
|
||||
/* Fields for DEPTH (Modulation depth percentage bits [20:21]) */
|
||||
#define FMPLL_SYNCR_DEPTH_0 0x00000000
|
||||
#define FMPLL_SYNCR_DEPTH_1 0x00000400
|
||||
#define FMPLL_SYNCR_DEPTH_2 0x00000800
|
||||
|
||||
/* Fields for EXP (Expected difference bits [22:31]) */
|
||||
#define FMPLL_SYNCR_EXP_0 0x00000000
|
||||
|
||||
/*
|
||||
* Definitions for the FMPLL_SYNSR (Synthesizer Status Register)
|
||||
*/
|
||||
|
||||
/* Fields for LOLF (Loss-of-lock flag bit [22]) */
|
||||
#define FMPLL_SYNSR_LOLF 0x00000200
|
||||
|
||||
/* Fields for LOCK (Lock status bit [28]) */
|
||||
#define FMPLL_SYNSR_LOCK 0x00000008
|
||||
|
||||
/* Fields for LOCF (Loss-of-clock flag bit [29]) */
|
||||
#define FMPLL_SYNSR_LOCF 0x00000004
|
||||
|
||||
/*
|
||||
* Definitions for the SIU_SRCR (System Reset Control Register)
|
||||
*/
|
||||
|
||||
/* Fields for SSR (software system reset bit [0]) */
|
||||
#define SIU_SRCR_SSR 0x80000000
|
||||
|
||||
/* Fields for SER (external system reset bit [1]) */
|
||||
#define SIU_SRCR_SER 0x40000000
|
||||
|
||||
/* Fields for CRE (checkstop reset enable bit [16]) */
|
||||
#define SIU_SRCR_CRE 0x00008000
|
||||
#if MPC55XX_CHIP_TYPE / 10 == 551
|
||||
#define FLASH_BIUCR 0xFFFF801C
|
||||
#else
|
||||
#define FLASH_BIUCR 0xC3F8801C
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Definitions for FLASH_BIUCR (Flash BIU Control Register)
|
||||
|
||||
@@ -165,6 +165,30 @@ extern "C" {
|
||||
} \
|
||||
}
|
||||
|
||||
#define MPC55XX_MMU_1K 0
|
||||
#define MPC55XX_MMU_2K 1
|
||||
#define MPC55XX_MMU_4K 2
|
||||
#define MPC55XX_MMU_8K 3
|
||||
#define MPC55XX_MMU_16K 4
|
||||
#define MPC55XX_MMU_32K 5
|
||||
#define MPC55XX_MMU_64K 6
|
||||
#define MPC55XX_MMU_128K 7
|
||||
#define MPC55XX_MMU_256K 8
|
||||
#define MPC55XX_MMU_512K 9
|
||||
#define MPC55XX_MMU_1M 10
|
||||
#define MPC55XX_MMU_2M 11
|
||||
#define MPC55XX_MMU_4M 12
|
||||
#define MPC55XX_MMU_8M 13
|
||||
#define MPC55XX_MMU_16M 14
|
||||
#define MPC55XX_MMU_32M 15
|
||||
#define MPC55XX_MMU_64M 16
|
||||
#define MPC55XX_MMU_128M 17
|
||||
#define MPC55XX_MMU_256M 18
|
||||
#define MPC55XX_MMU_512M 19
|
||||
#define MPC55XX_MMU_1G 20
|
||||
#define MPC55XX_MMU_2G 21
|
||||
#define MPC55XX_MMU_4G 22
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
@@ -30,12 +30,40 @@
|
||||
|
||||
#if MPC55XX_CHIP_TYPE / 10 == 551
|
||||
#include <mpc55xx/fsl-mpc551x.h>
|
||||
#define MPC55XX_HAS_EBI
|
||||
#define MPC55XX_HAS_ESCI
|
||||
#define MPC55XX_HAS_EMIOS
|
||||
#define MPC55XX_HAS_FMPLL_ENHANCED
|
||||
#elif MPC55XX_CHIP_TYPE / 10 == 555
|
||||
#include <mpc55xx/fsl-mpc555x.h>
|
||||
#define MPC55XX_HAS_EBI
|
||||
#define MPC55XX_HAS_ESCI
|
||||
#define MPC55XX_HAS_EMIOS
|
||||
#define MPC55XX_HAS_FMPLL
|
||||
#define MPC55XX_HAS_UNIFIED_CACHE
|
||||
#elif MPC55XX_CHIP_TYPE / 10 == 556
|
||||
#include <mpc55xx/fsl-mpc556x.h>
|
||||
#define MPC55XX_HAS_EBI
|
||||
#define MPC55XX_HAS_ESCI
|
||||
#define MPC55XX_HAS_EMIOS
|
||||
#define MPC55XX_HAS_FMPLL
|
||||
#define MPC55XX_HAS_UNIFIED_CACHE
|
||||
#elif MPC55XX_CHIP_TYPE / 10 == 564
|
||||
#include <mpc55xx/fsl-mpc564xL.h>
|
||||
#define MPC55XX_HAS_STM
|
||||
#define MPC55XX_HAS_SWT
|
||||
#define MPC55XX_HAS_MODE_CONTROL
|
||||
#define MPC55XX_HAS_INSTRUCTION_CACHE
|
||||
#define MPC55XX_HAS_LINFLEX
|
||||
#define MPC55XX_HAS_SECOND_INTERNAL_RAM_AREA
|
||||
#elif MPC55XX_CHIP_TYPE / 10 == 567
|
||||
#include <mpc55xx/fsl-mpc567x.h>
|
||||
#define MPC55XX_HAS_EBI
|
||||
#define MPC55XX_HAS_ESCI
|
||||
#define MPC55XX_HAS_EMIOS
|
||||
#define MPC55XX_HAS_FMPLL_ENHANCED
|
||||
#define MPC55XX_HAS_INSTRUCTION_CACHE
|
||||
#define MPC55XX_HAS_DATA_CACHE
|
||||
#else
|
||||
#error "unsupported chip type"
|
||||
#endif
|
||||
|
||||
@@ -1,112 +0,0 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup mpc55xx_asm
|
||||
*
|
||||
* @brief Flash configuration.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <libcpu/powerpc-utility.h>
|
||||
#include <mpc55xx/reg-defs.h>
|
||||
|
||||
.section ".bsp_start_text", "ax"
|
||||
|
||||
/* Optimized flash configurations (Table 13-15 [MPC5567 Microcontroller Reference Manual]) */
|
||||
.equ FLASH_SETTINGS_RESET, 0xff00
|
||||
.equ FLASH_SETTINGS_82, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_1 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN
|
||||
.equ FLASH_SETTINGS_102, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_2 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN
|
||||
.equ FLASH_SETTINGS_132, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_2 | FLASH_BUICR_RWSC_3 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN
|
||||
.equ FLASH_SETTINGS_264, 0x01716B15
|
||||
|
||||
/**
|
||||
* @fn void mpc55xx_flash_init()
|
||||
* @brief Optimized flash configuration.
|
||||
* @warning Code will be copied and executed on the stack. The stack pointer
|
||||
* will not be updated, since this function has to work before memory
|
||||
* initialization.
|
||||
*/
|
||||
GLOBAL_FUNCTION mpc55xx_flash_init
|
||||
mflr r31
|
||||
|
||||
/* Flash settings dependent on system clock */
|
||||
bl mpc55xx_get_system_clock
|
||||
LWI r4, 82000000
|
||||
cmpw r3, r4
|
||||
ble clock_82
|
||||
LWI r4, 102000000
|
||||
cmpw r3, r4
|
||||
ble clock_102
|
||||
LWI r4, 132000000
|
||||
cmpw r3, r4
|
||||
ble clock_132
|
||||
LWI r4, 264000000
|
||||
cmpw r3, r4
|
||||
ble clock_264
|
||||
LWI r30, FLASH_SETTINGS_RESET
|
||||
b settings_done
|
||||
clock_82:
|
||||
LWI r30, FLASH_SETTINGS_82
|
||||
b settings_done
|
||||
clock_102:
|
||||
LWI r30, FLASH_SETTINGS_102
|
||||
b settings_done
|
||||
clock_132:
|
||||
LWI r30, FLASH_SETTINGS_132
|
||||
b settings_done
|
||||
clock_264:
|
||||
LWI r30, FLASH_SETTINGS_264
|
||||
b settings_done
|
||||
settings_done:
|
||||
|
||||
/* Copy store code on the stack */
|
||||
LA r3, store_start
|
||||
LA r5, store_end
|
||||
subf r5, r3, r5
|
||||
subf r4, r5, r1
|
||||
|
||||
/* Assert: Proper alignment of destination start */
|
||||
andi. r6, r4, 0x7
|
||||
bne twiddle
|
||||
|
||||
/* Copy */
|
||||
bl mpc55xx_copy_8
|
||||
|
||||
LA r6, FLASH_BIUCR
|
||||
|
||||
/* Execute store code */
|
||||
mtctr r4
|
||||
bctrl
|
||||
|
||||
mtlr r31
|
||||
blr
|
||||
|
||||
/*
|
||||
* Store flash settings
|
||||
*/
|
||||
|
||||
.align 3
|
||||
.set store_start, .
|
||||
stw r30, 0(r6)
|
||||
isync
|
||||
blr
|
||||
.align 3
|
||||
.set store_end, .
|
||||
|
||||
twiddle:
|
||||
b twiddle
|
||||
@@ -1,193 +0,0 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup mpc55xx_asm
|
||||
*
|
||||
* @brief FMPLL setup.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <libcpu/powerpc-utility.h>
|
||||
#include <mpc55xx/reg-defs.h>
|
||||
#include <bspopts.h>
|
||||
|
||||
#define FMPLL_IS_MPC551X (5510 <= MPC55XX_CHIP_TYPE && MPC55XX_CHIP_TYPE <= 5517)
|
||||
|
||||
#define FMPLL_IS_MPC5674 (MPC55XX_CHIP_TYPE == 5674)
|
||||
|
||||
#define FMPLL_HAS_ENHANCED_FMPLL (FMPLL_IS_MPC551X || FMPLL_IS_MPC5674)
|
||||
|
||||
.section ".bsp_start_text", "ax"
|
||||
|
||||
/* Timeout for delay in clocks */
|
||||
.equ FMPLL_TIMEOUT, 6000
|
||||
|
||||
.macro DO_SETTING setting
|
||||
lwz r5, \setting
|
||||
stw r5, 0(r4)
|
||||
msync
|
||||
bl fmpll_wait_for_lock
|
||||
.endm
|
||||
|
||||
/**
|
||||
* @fn void mpc55xx_fmpll_init()
|
||||
* @brief Configure FMPLL after reset.
|
||||
*/
|
||||
GLOBAL_FUNCTION mpc55xx_fmpll_init
|
||||
/* Save link register */
|
||||
mflr r9
|
||||
|
||||
#if FMPLL_HAS_ENHANCED_FMPLL
|
||||
/*
|
||||
* for MPC5510: pass in ptr to array with:
|
||||
* off 0: temp setting for ESYNCR2
|
||||
* off 4: final setting for ESYNCR2
|
||||
* off 8: final setting for ESYNCR1
|
||||
*/
|
||||
LA r4, FMPLL_ESYNCR2
|
||||
|
||||
lwz r5, 0(r3)
|
||||
stw r5, 0(r4)
|
||||
msync
|
||||
|
||||
lwz r5, 8(r3)
|
||||
stw r5, (FMPLL_ESYNCR1-FMPLL_ESYNCR2)(r4)
|
||||
msync
|
||||
bl fmpll_wait_for_lock
|
||||
|
||||
DO_SETTING 4(r3)
|
||||
|
||||
#if FMPLL_IS_MPC551X
|
||||
/*
|
||||
* switch to PLL clock in SIU
|
||||
*/
|
||||
LA r4, SIU_SYSCLK
|
||||
lwz r5, 0(r4)
|
||||
LWI r6, ~SIU_SYSCLK_SYSCLKSEL_MASK
|
||||
and r5, r5, r6
|
||||
LWI r6, SIU_SYSCLK_SYSCLKSEL_PLL
|
||||
or r5, r5, r6
|
||||
stw r5, 0(r4)
|
||||
#endif /* FMPLL_IS_MPC551X */
|
||||
#else /* !FMPLL_HAS_ENHANCED_FMPLL */
|
||||
/*
|
||||
* for MPC5566: pass in ptr to array with:
|
||||
* off 0: temp setting for SYNCR
|
||||
* off 4: final setting for SYNCR
|
||||
*/
|
||||
|
||||
LA r4, FMPLL_SYNCR
|
||||
|
||||
DO_SETTING 0(r3)
|
||||
DO_SETTING 4(r3)
|
||||
|
||||
/* Enable loss-of-clock and loss-of-lock IRQs */
|
||||
lwz r5, 0(r4)
|
||||
LWI r6, FMPLL_SYNCR_LOCIRQ | FMPLL_SYNCR_LOLIRQ
|
||||
or r5, r5, r6
|
||||
|
||||
/* Disable loss-of-clock and loss-of-lock resets */
|
||||
LWI r6, ~FMPLL_SYNCR_LOCRE & ~FMPLL_SYNCR_LOLRE
|
||||
and r5, r5, r6
|
||||
stw r5, 0(r4)
|
||||
#endif /* !FMPLL_HAS_ENHANCED_FMPLL */
|
||||
|
||||
/* Restore link register and return */
|
||||
mtlr r9
|
||||
blr
|
||||
|
||||
fmpll_wait_for_lock:
|
||||
LWI r6, FMPLL_TIMEOUT
|
||||
mtctr r6
|
||||
|
||||
LWI r7, FMPLL_SYNSR_LOCK
|
||||
|
||||
LA r6, FMPLL_SYNSR
|
||||
|
||||
fmpll_not_locked:
|
||||
bdnz fmpll_continue
|
||||
|
||||
b mpc55xx_system_reset
|
||||
fmpll_continue:
|
||||
lwz r5, 0(r6)
|
||||
and. r5, r5, r7
|
||||
beq fmpll_not_locked
|
||||
|
||||
blr
|
||||
|
||||
.section ".text", "aw"
|
||||
|
||||
/**
|
||||
* @fn int mpc55xx_get_system_clock()
|
||||
* @brief Returns the system clock.
|
||||
*/
|
||||
GLOBAL_FUNCTION mpc55xx_get_system_clock
|
||||
#if FMPLL_HAS_ENHANCED_FMPLL
|
||||
LA r4, FMPLL_ESYNCR1
|
||||
lwz r3, 0(r4)
|
||||
/* EPREDIV */
|
||||
rlwinm r5, r3,16, 28, 31
|
||||
|
||||
/* MFD */
|
||||
rlwinm r6, r3,0, 24, 31
|
||||
|
||||
LA r4, FMPLL_ESYNCR2
|
||||
lwz r3, 0(r4)
|
||||
/* ERFD */
|
||||
rlwinm r7, r3,0, 26, 31
|
||||
|
||||
LWI r8, MPC55XX_FMPLL_REF_CLOCK
|
||||
addi r5, r5, 1
|
||||
addi r6, r6,16
|
||||
addi r7, r7, 1
|
||||
divw r3, r8, r5 /* REF_CLOCK/PREDIV */
|
||||
mullw r3, r6, r3 /* REF_CLOCK/PREDIV*MFD */
|
||||
divw r3, r3, r7 /* REF_CLOCK/PREDIV*MFD/RFD */
|
||||
#else /* !FMPLL_HAS_ENHANCED_FMPLL */
|
||||
LA r4, FMPLL_SYNCR
|
||||
lwz r3, 0(r4)
|
||||
|
||||
/* PREDIV */
|
||||
rlwinm r5, r3, 4, 29, 31
|
||||
|
||||
/* MFD */
|
||||
rlwinm r6, r3, 9, 27, 31
|
||||
|
||||
/* RFD */
|
||||
rlwinm r7, r3, 13, 29, 31
|
||||
/* Calculate system clock (Table 11-10 [MPC5567 Microcontroller Reference Manual]) */
|
||||
LWI r8, MPC55XX_FMPLL_REF_CLOCK
|
||||
addi r5, r5, 1
|
||||
addi r6, r6, 4
|
||||
mullw r6, r6, r8
|
||||
sraw r6, r6, r7
|
||||
divw r3, r6, r5
|
||||
#endif /* !FMPLL_HAS_ENHANCED_FMPLL */
|
||||
|
||||
blr
|
||||
|
||||
/**
|
||||
* @fn void mpc55xx_system_reset()
|
||||
* @brief Software system reset.
|
||||
*/
|
||||
GLOBAL_FUNCTION mpc55xx_system_reset
|
||||
LA r8, SIU_SRCR
|
||||
LWI r9, SIU_SRCR_SSR
|
||||
stw r9, 0(r8)
|
||||
twiddle:
|
||||
b twiddle
|
||||
@@ -274,6 +274,7 @@ const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu)
|
||||
return &e500_category_table;
|
||||
case PPC_e200z0:
|
||||
case PPC_e200z1:
|
||||
case PPC_e200z4:
|
||||
case PPC_e200z6:
|
||||
case PPC_e200z7:
|
||||
return &e200_category_table;
|
||||
|
||||
@@ -270,10 +270,6 @@ $(PROJECT_INCLUDE)/mpc55xx/mpc55xx.h: mpc55xx/include/mpc55xx.h $(PROJECT_INCLUD
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/mpc55xx.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/mpc55xx.h
|
||||
|
||||
$(PROJECT_INCLUDE)/mpc55xx/esci.h: mpc55xx/include/esci.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/esci.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/esci.h
|
||||
|
||||
$(PROJECT_INCLUDE)/mpc55xx/siu.h: mpc55xx/include/siu.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/siu.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/siu.h
|
||||
@@ -298,6 +294,10 @@ $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc556x.h: mpc55xx/include/fsl-mpc556x.h $(PROJEC
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc556x.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc556x.h
|
||||
|
||||
$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc564xL.h: mpc55xx/include/fsl-mpc564xL.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc564xL.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc564xL.h
|
||||
|
||||
$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc567x.h: mpc55xx/include/fsl-mpc567x.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc567x.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc567x.h
|
||||
|
||||
@@ -53,6 +53,7 @@ const char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu)
|
||||
case PPC_PSIM: return "PSIM";
|
||||
case PPC_e200z0: return "e200z0";
|
||||
case PPC_e200z1: return "e200z1";
|
||||
case PPC_e200z4: return "e200z4";
|
||||
case PPC_e200z6: return "e200z6";
|
||||
case PPC_e200z7: return "e200z7";
|
||||
case PPC_e500v2: return "e500v2";
|
||||
@@ -72,6 +73,7 @@ ppc_cpu_id_t get_ppc_cpu_type(void)
|
||||
const uint32_t ppc_cpu_id_version_nibble[] = {
|
||||
PPC_e200z0,
|
||||
PPC_e200z1,
|
||||
PPC_e200z4,
|
||||
PPC_e200z6,
|
||||
PPC_e200z7
|
||||
};
|
||||
@@ -122,6 +124,7 @@ ppc_cpu_id_t get_ppc_cpu_type(void)
|
||||
case PPC_8540:
|
||||
case PPC_e200z0:
|
||||
case PPC_e200z1:
|
||||
case PPC_e200z4:
|
||||
case PPC_e200z6:
|
||||
case PPC_e200z7:
|
||||
case PPC_e300c1:
|
||||
@@ -182,6 +185,7 @@ ppc_cpu_id_t get_ppc_cpu_type(void)
|
||||
case PPC_8540:
|
||||
case PPC_e200z0:
|
||||
case PPC_e200z1:
|
||||
case PPC_e200z4:
|
||||
case PPC_e200z6:
|
||||
case PPC_e200z7:
|
||||
case PPC_e500v2:
|
||||
|
||||
@@ -58,6 +58,7 @@ typedef enum
|
||||
PPC_e300c3 = 0x8085, /* e300c3 core */
|
||||
PPC_e200z0 = 0x8170,
|
||||
PPC_e200z1 = 0x8140,
|
||||
PPC_e200z4 = 0x8155,
|
||||
PPC_e200z6 = 0x8110,
|
||||
PPC_e200z7 = 0x8160,
|
||||
PPC_PSIM = 0xfffe, /* GDB PowerPC simulator -- fake version */
|
||||
|
||||
Reference in New Issue
Block a user