forked from Imagelibrary/rtems
2007-11-29 Till Straumann <strauman@slac.stanford.edu>
* startup/bspstart.c, Makefile.am: Initialize BATs and enable MMU to come closer to what other BSPs do. This allows us to use the shared irq_asm.S. No more individual assembly code :-)
This commit is contained in:
Till Straumann
@@ -1,3 +1,9 @@
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2007-11-29 Till Straumann <strauman@slac.stanford.edu>
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* startup/bspstart.c, Makefile.am: Initialize BATs and enable MMU
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to come closer to what other BSPs do. This allows us to use the
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shared irq_asm.S. No more individual assembly code :-)
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2007-11-28 Joel Sherrill <joel.sherrill@OARcorp.com>
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2007-11-28 Joel Sherrill <joel.sherrill@OARcorp.com>
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* startup/bspstart.c: Eliminate PowerPC specific elements from the CPU
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* startup/bspstart.c: Eliminate PowerPC specific elements from the CPU
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@@ -65,7 +65,7 @@ consoleio_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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include_bsp_HEADERS = irq/irq.h
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include_bsp_HEADERS = irq/irq.h
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noinst_PROGRAMS += irq.rel
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noinst_PROGRAMS += irq.rel
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irq_rel_SOURCES = irq/irq.c irq/irq_init.c irq/irq_asm.S
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irq_rel_SOURCES = irq/irq.c irq/irq_init.c ../shared/irq/irq_asm.S
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irq_rel_CPPFLAGS = $(AM_CPPFLAGS)
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irq_rel_CPPFLAGS = $(AM_CPPFLAGS)
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irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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@@ -1,357 +0,0 @@
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/*
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* This file contains the assembly code for the PowerPC
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* IRQ veneers for RTEMS.
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* Modified to support the MCP750.
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* Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
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*
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* Till Straumann <strauman@slac.stanford.edu>, 2003/7:
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* - store isr nesting level in _ISR_Nest_level rather than
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* SPRG0 - RTEMS relies on that variable.
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*
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* irq_asm.S,v 1.5.4.3 2003/09/04 18:45:20 joel Exp
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*/
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#include <rtems/asm.h>
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#include <rtems/score/cpu.h>
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#include <bsp/vectors.h>
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#include <libcpu/raw_exception.h>
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#define SYNC \
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sync; \
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isync
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.text
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.p2align 5
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PUBLIC_VAR(decrementer_exception_vector_prolog_code)
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SYM (decrementer_exception_vector_prolog_code):
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/*
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* let room for exception frame
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*/
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stwu r1, - (EXCEPTION_FRAME_END)(r1)
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stw r4, GPR4_OFFSET(r1)
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li r4, ASM_DEC_VECTOR
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ba shared_raw_irq_code_entry
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PUBLIC_VAR (decrementer_exception_vector_prolog_code_size)
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decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code
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PUBLIC_VAR(external_exception_vector_prolog_code)
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SYM (external_exception_vector_prolog_code):
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/*
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* let room for exception frame
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*/
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stwu r1, - (EXCEPTION_FRAME_END)(r1)
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stw r4, GPR4_OFFSET(r1)
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li r4, ASM_EXT_VECTOR
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ba shared_raw_irq_code_entry
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PUBLIC_VAR (external_exception_vector_prolog_code_size)
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external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code
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PUBLIC_VAR(shared_raw_irq_code_entry)
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PUBLIC_VAR(C_dispatch_irq_handler)
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.p2align 5
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SYM (shared_raw_irq_code_entry):
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/*
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* Entry conditions :
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* Registers already saved : R1, R4
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* R1 : points to a location with enough room for the
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* interrupt frame
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* R4 : vector number
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*/
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/*
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* Save SRR0/SRR1 As soon As possible as it is the minimal needed
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* to reenable exception processing
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*/
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stw r0, GPR0_OFFSET(r1)
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/* PPC EABI: R2 is reserved (pointer to short data .sdata2) - we won't touch it
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* but we still save/restore it, just in case...
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*/
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stw r2, GPR2_OFFSET(r1)
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stw r3, GPR3_OFFSET(r1)
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mfsrr0 r0
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mfsrr1 r3
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stw r0, SRR0_FRAME_OFFSET(r1)
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stw r3, SRR1_FRAME_OFFSET(r1)
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mfmsr r3
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/*
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* Enable data and instruction address translation, exception recovery
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*
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* also, on CPUs with FP, enable FP so that FP context can be
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* saved and restored (using FP instructions)
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*/
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#if (PPC_HAS_FPU == 0)
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ori r3, r3, MSR_RI | MSR_IR | MSR_DR
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#else
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ori r3, r3, MSR_RI | MSR_FP /* MSR_IR | MSR_DR */
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#endif
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mtmsr r3
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SYNC
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/*
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* Push C scratch registers on the current stack. It may
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* actually be the thread stack or the interrupt stack.
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* Anyway we have to make it in order to be able to call C/C++
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* functions. Depending on the nesting interrupt level, we will
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* switch to the right stack later.
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*/
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stw r5, GPR5_OFFSET(r1)
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stw r6, GPR6_OFFSET(r1)
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stw r7, GPR7_OFFSET(r1)
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stw r8, GPR8_OFFSET(r1)
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stw r9, GPR9_OFFSET(r1)
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stw r10, GPR10_OFFSET(r1)
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stw r11, GPR11_OFFSET(r1)
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stw r12, GPR12_OFFSET(r1)
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stw r13, GPR13_OFFSET(r1)
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mfcr r5
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mfctr r6
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mfxer r7
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mflr r8
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stw r5, EXC_CR_OFFSET(r1)
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stw r6, EXC_CTR_OFFSET(r1)
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stw r7, EXC_XER_OFFSET(r1)
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stw r8, EXC_LR_OFFSET(r1)
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/*
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* Add some non volatile registers to store information
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* that will be used when returning from C handler
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*/
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stw r14, GPR14_OFFSET(r1)
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stw r15, GPR15_OFFSET(r1)
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/*
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* save current stack pointer location in R14
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*/
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addi r14, r1, 0
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/*
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* store part of _Thread_Dispatch_disable_level address in R15
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*/
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addis r15,0, _Thread_Dispatch_disable_level@ha
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#if BROKEN_ISR_NEST_LEVEL
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/*
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* Get current nesting level in R3
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*/
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mfspr r3, SPRG0
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#else
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/*
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* Retrieve current nesting level from _ISR_Nest_level
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*/
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lis r7, _ISR_Nest_level@ha
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lwz r3, _ISR_Nest_level@l(r7)
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#endif
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/*
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* Check if stack switch is necessary
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*/
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cmpwi r3,0
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bne nested
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mfspr r1, SPRG1
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nested:
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/*
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* Start Incrementing nesting level in R3
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*/
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addi r3,r3,1
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/*
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* Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
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*/
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lwz r6,_Thread_Dispatch_disable_level@l(r15)
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#if BROKEN_ISR_NEST_LEVEL
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/*
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* Store new nesting level in SPRG0
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*/
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mtspr SPRG0, r3
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#else
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/* store new nesting level in _ISR_Nest_level */
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stw r3, _ISR_Nest_level@l(r7)
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#endif
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addi r6, r6, 1
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mfmsr r5
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/*
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* store new _Thread_Dispatch_disable_level value
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*/
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stw r6, _Thread_Dispatch_disable_level@l(r15)
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/*
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* We are now running on the interrupt stack. External and decrementer
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* exceptions are still disabled. I see no purpose trying to optimize
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* further assembler code.
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*/
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/*
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* Call C exception handler for decrementer Interrupt frame is passed just
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* in case...
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*/
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addi r3, r14, 0x8
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bl C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */
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/*
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* start decrementing nesting level. Note : do not test result against 0
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* value as an easy exit condition because if interrupt nesting level > 1
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* then _Thread_Dispatch_disable_level > 1
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*/
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#if BROKEN_ISR_NEST_LEVEL
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mfspr r4, SPRG0
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#else
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lis r7, _ISR_Nest_level@ha
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lwz r4, _ISR_Nest_level@l(r7)
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#endif
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/*
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* start decrementing _Thread_Dispatch_disable_level
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*/
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lwz r3,_Thread_Dispatch_disable_level@l(r15)
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addi r4, r4, -1 /* Continue decrementing nesting level */
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addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */
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#if BROKEN_ISR_NEST_LEVEL
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mtspr SPRG0, r4 /* End decrementing nesting level */
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#else
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stw r4, _ISR_Nest_level@l(r7) /* End decrementing nesting level */
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#endif
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stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
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cmpwi r3, 0
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/*
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* switch back to original stack (done here just optimize registers
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* contention. Could have been done before...)
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*/
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addi r1, r14, 0
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bne easy_exit /* if (_Thread_Dispatch_disable_level != 0) goto easy_exit */
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/*
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* Here we are running again on the thread system stack.
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* We have interrupt nesting level = _Thread_Dispatch_disable_level = 0.
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* Interrupt are still disabled. Time to check if scheduler request to
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* do something with the current thread...
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*/
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addis r4, 0, _Context_Switch_necessary@ha
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lwz r5, _Context_Switch_necessary@l(r4)
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cmpwi r5, 0
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bne switch
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addis r6, 0, _ISR_Signals_to_thread_executing@ha
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lwz r7, _ISR_Signals_to_thread_executing@l(r6)
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cmpwi r7, 0
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li r8, 0
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beq easy_exit
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stw r8, _ISR_Signals_to_thread_executing@l(r6)
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|
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/*
|
|
||||||
* going to call _ThreadProcessSignalsFromIrq
|
|
||||||
* Push a complete exception like frame...
|
|
||||||
*/
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|
||||||
stmw r16, GPR16_OFFSET(r1)
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addi r3, r1, 0x8
|
|
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/*
|
|
||||||
* compute SP at exception entry
|
|
||||||
*/
|
|
||||||
addi r4, r1, EXCEPTION_FRAME_END
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|
||||||
/*
|
|
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* store it at the right place
|
|
||||||
*/
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|
||||||
stw r4, GPR1_OFFSET(r1)
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|
||||||
/*
|
|
||||||
* Call High Level signal handling code
|
|
||||||
*/
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|
||||||
bl _ThreadProcessSignalsFromIrq
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|
||||||
/*
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|
||||||
* start restoring exception like frame
|
|
||||||
*/
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|
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lwz r31, EXC_CTR_OFFSET(r1)
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|
||||||
lwz r30, EXC_XER_OFFSET(r1)
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|
||||||
lwz r29, EXC_CR_OFFSET(r1)
|
|
||||||
lwz r28, EXC_LR_OFFSET(r1)
|
|
||||||
|
|
||||||
mtctr r31
|
|
||||||
mtxer r30
|
|
||||||
mtcr r29
|
|
||||||
mtlr r28
|
|
||||||
|
|
||||||
lmw r4, GPR4_OFFSET(r1)
|
|
||||||
lwz r2, GPR2_OFFSET(r1)
|
|
||||||
lwz r0, GPR0_OFFSET(r1)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Disable data and instruction translation. Make path non recoverable...
|
|
||||||
*/
|
|
||||||
mfmsr r3
|
|
||||||
xori r3, r3, MSR_RI /* | MSR_IR | MSR_DR */
|
|
||||||
mtmsr r3
|
|
||||||
SYNC
|
|
||||||
/*
|
|
||||||
* Restore rfi related settings
|
|
||||||
*/
|
|
||||||
|
|
||||||
lwz r3, SRR1_FRAME_OFFSET(r1)
|
|
||||||
mtsrr1 r3
|
|
||||||
lwz r3, SRR0_FRAME_OFFSET(r1)
|
|
||||||
mtsrr0 r3
|
|
||||||
|
|
||||||
lwz r3, GPR3_OFFSET(r1)
|
|
||||||
addi r1,r1, EXCEPTION_FRAME_END
|
|
||||||
SYNC
|
|
||||||
rfi
|
|
||||||
|
|
||||||
switch:
|
|
||||||
bl SYM (_Thread_Dispatch)
|
|
||||||
|
|
||||||
easy_exit:
|
|
||||||
/*
|
|
||||||
* start restoring interrupt frame
|
|
||||||
*/
|
|
||||||
lwz r3, EXC_CTR_OFFSET(r1)
|
|
||||||
lwz r4, EXC_XER_OFFSET(r1)
|
|
||||||
lwz r5, EXC_CR_OFFSET(r1)
|
|
||||||
lwz r6, EXC_LR_OFFSET(r1)
|
|
||||||
|
|
||||||
mtctr r3
|
|
||||||
mtxer r4
|
|
||||||
mtcr r5
|
|
||||||
mtlr r6
|
|
||||||
|
|
||||||
lwz r15, GPR15_OFFSET(r1)
|
|
||||||
lwz r14, GPR14_OFFSET(r1)
|
|
||||||
lwz r13, GPR13_OFFSET(r1)
|
|
||||||
lwz r12, GPR12_OFFSET(r1)
|
|
||||||
lwz r11, GPR11_OFFSET(r1)
|
|
||||||
lwz r10, GPR10_OFFSET(r1)
|
|
||||||
lwz r9, GPR9_OFFSET(r1)
|
|
||||||
lwz r8, GPR8_OFFSET(r1)
|
|
||||||
lwz r7, GPR7_OFFSET(r1)
|
|
||||||
lwz r6, GPR6_OFFSET(r1)
|
|
||||||
lwz r5, GPR5_OFFSET(r1)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Disable nested exception processing, data and instruction
|
|
||||||
* translation.
|
|
||||||
*/
|
|
||||||
mfmsr r3
|
|
||||||
xori r3, r3, MSR_RI /* | MSR_IR | MSR_DR */
|
|
||||||
mtmsr r3
|
|
||||||
SYNC
|
|
||||||
/*
|
|
||||||
* Restore rfi related settings
|
|
||||||
*/
|
|
||||||
|
|
||||||
lwz r4, SRR1_FRAME_OFFSET(r1)
|
|
||||||
lwz r3, SRR0_FRAME_OFFSET(r1)
|
|
||||||
lwz r2, GPR2_OFFSET(r1)
|
|
||||||
lwz r0, GPR0_OFFSET(r1)
|
|
||||||
|
|
||||||
mtsrr1 r4
|
|
||||||
mtsrr0 r3
|
|
||||||
lwz r4, GPR4_OFFSET(r1)
|
|
||||||
lwz r3, GPR3_OFFSET(r1)
|
|
||||||
addi r1,r1, EXCEPTION_FRAME_END
|
|
||||||
SYNC
|
|
||||||
rfi
|
|
||||||
|
|
||||||
@@ -24,6 +24,7 @@
|
|||||||
#include <rtems/powerpc/powerpc.h>
|
#include <rtems/powerpc/powerpc.h>
|
||||||
|
|
||||||
#include <libcpu/cpuIdent.h>
|
#include <libcpu/cpuIdent.h>
|
||||||
|
#include <libcpu/bat.h>
|
||||||
#include <libcpu/spr.h>
|
#include <libcpu/spr.h>
|
||||||
|
|
||||||
SPR_RW(SPRG0)
|
SPR_RW(SPRG0)
|
||||||
@@ -226,4 +227,17 @@ void bsp_start( void )
|
|||||||
*/
|
*/
|
||||||
BSP_rtems_irq_mng_init(0);
|
BSP_rtems_irq_mng_init(0);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Setup BATs and enable MMU
|
||||||
|
*/
|
||||||
|
/* Memory */
|
||||||
|
setdbat(0, 0x0<<24, 0x0<<24, 1<<24, _PAGE_RW);
|
||||||
|
setibat(0, 0x0<<24, 0x0<<24, 1<<24, 0);
|
||||||
|
/* PCI */
|
||||||
|
setdbat(1, 0x8<<24, 0x8<<24, 1<<24, IO_PAGE);
|
||||||
|
setdbat(2, 0xc<<24, 0xc<<24, 1<<24, IO_PAGE);
|
||||||
|
|
||||||
|
_write_MSR(_read_MSR() | MSR_DR | MSR_IR);
|
||||||
|
asm volatile("sync; isync");
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|||||||
Reference in New Issue
Block a user