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2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>

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* clock/clock.c, startup/bspstart.c, startup/init5282.c:
	Use "__asm__" instead of "asm" for improved c99-compliance.
This commit is contained in:
Ralf Corsepius
2011-02-11 12:34:18 +00:00
parent c3b18f9f21
commit a571938285
4 changed files with 16 additions and 11 deletions
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5
c/src/lib/libbsp/m68k/uC5282/ChangeLog
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@@ -1,3 +1,8 @@
2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>
* clock/clock.c, startup/bspstart.c, startup/init5282.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
2011-02-09 Ralf Corsépius <ralf.corsepius@rtems.org> 2011-02-09 Ralf Corsépius <ralf.corsepius@rtems.org>
* timer/timer.c: Include <rtems/btimer.h>. * timer/timer.c: Include <rtems/btimer.h>.

2
c/src/lib/libbsp/m68k/uC5282/clock/clock.c
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@@ -115,7 +115,7 @@ uint32_t bsp_clock_nanoseconds_since_last_tick(void)
Thread bsp_idle_thread(uint32_t ignored) Thread bsp_idle_thread(uint32_t ignored)
{ {
for(;;) for(;;)
asm volatile ("addq.l #1,__SRAMBASE"); /* Atomic increment */ __asm__ volatile ("addq.l #1,__SRAMBASE"); /* Atomic increment */
} }
int rtems_bsp_cpu_load_percentage(void) int rtems_bsp_cpu_load_percentage(void)

14
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
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@@ -75,10 +75,10 @@ extern char RamBase[];
* ACRn[5] = BUFW (buffered write enable) must be 0 * ACRn[5] = BUFW (buffered write enable) must be 0
* Fix plan: Currently, there are no plans to fix this. * Fix plan: Currently, there are no plans to fix this.
*/ */
#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr)) #define m68k_set_cacr_nop(_cacr) __asm__ volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr)) #define m68k_set_cacr(_cacr) __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) #define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0))
#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) #define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1))
/* /*
* Read/write copy of cache registers * Read/write copy of cache registers
@@ -140,7 +140,7 @@ void _CPU_cache_invalidate_1_instruction_line(const void *addr)
* Top half of cache is I-space * Top half of cache is I-space
*/ */
addr = (void *)((int)addr | 0x400); addr = (void *)((int)addr | 0x400);
asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
} }
void _CPU_cache_enable_data(void) void _CPU_cache_enable_data(void)
@@ -181,7 +181,7 @@ void _CPU_cache_invalidate_1_data_line(const void *addr)
* Bottom half of cache is D-space * Bottom half of cache is D-space
*/ */
addr = (void *)((int)addr & ~0x400); addr = (void *)((int)addr & ~0x400);
asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
#endif #endif
} }
@@ -415,7 +415,7 @@ syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode
/* reset-control register */ /* reset-control register */
#define RCR "__IPSBAR + 0x110000" #define RCR "__IPSBAR + 0x110000"
asm( __asm__ (
"bsp_fake_syscall: \n" "bsp_fake_syscall: \n"
" cmpl #0, %d0 \n" /* sysreset */ " cmpl #0, %d0 \n" /* sysreset */
" bne 1f \n" " bne 1f \n"

6
c/src/lib/libbsp/m68k/uC5282/startup/init5282.c
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@@ -19,9 +19,9 @@
#include <rtems.h> #include <rtems.h>
#include <bsp.h> #include <bsp.h>
#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr)) #define m68k_set_cacr(_cacr) __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) #define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0))
#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) #define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1))
extern void CopyDataClearBSSAndStart (void); extern void CopyDataClearBSSAndStart (void);