Added a special CPU model of "rtems_multilib". This is the beginnings

of an experiment to determine what it will take to multilib most of
RTEMS per GNU multilib conventions.  It is thought that only
interrupt processing and IO are not multlib-able.  This means that
a BSP Kit should include IRQ processing from score/cpu, all peripheral
support (header files from score/cpu, libchip, and libcpu), and the
BSPs themselves.  The rest of RTEMS should be multlib-able.  But to do
this, all RTEMS CPU model feature flags must be derivable from gcc
cpp predefines.  By configuring the bare bsp with the rtems_multilib
CPU model, you can try any combination of CPU CFLAGS and see well how the
logic in that section of the <CPU>.h works.   Once all CPU multilib
variations can be built, then RTEMS proper can be multilib'ed and
separated from the BSPs.
This commit is contained in:
Joel Sherrill
2000-05-28 20:14:45 +00:00
parent 63cf252f31
commit a3f5b6be31
11 changed files with 126 additions and 10 deletions

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@@ -28,7 +28,16 @@ extern "C" {
* of the family.
*/
#if defined(a29205)
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define A29K_HAS_FPU 0
#elif defined(a29205)
#define CPU_MODEL_NAME "a29205"
#define A29K_HAS_FPU 0

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@@ -35,7 +35,15 @@ extern "C" {
* present in a particular member of the family.
*/
#if defined(hppa7100)
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#elif defined(hppa7100)
#define CPU_MODEL_NAME "hppa 7100"

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@@ -46,7 +46,17 @@ extern "C" {
*
*/
#if defined(i386_fp)
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define I386_HAS_FPU 0
#define I386_HAS_BSWAP 0
#elif defined(i386_fp)
#define CPU_MODEL_NAME "i386 with i387"
#define I386_HAS_BSWAP 0

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@@ -33,7 +33,18 @@ extern "C" {
* NOTE: RTEMS defines a canonical name for each cpu model.
*/
#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define I960_HAS_FPU 0
#define I960_CPU_ALIGNMENT 4
#define I960_SOFT_RESET_COMMAND 0x30000
#elif defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
#define CPU_MODEL_NAME "i960ca"
#define __RTEMS_I960CA__

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@@ -79,6 +79,15 @@ extern "C" {
* by having each model specify which core it uses and then go from there.
*/
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines. Notice the only exception to this is that
* gcc does not distinguish between CPU32 and CPU32+. This
* feature selection logic is setup such that if RTEMS__mcpu32p__
* is defined, then CPU32+ rules are used. Otherwise, the safe
* but less efficient CPU32 rules are used for the CPU32+.
*/
#if defined(__mc68020__)
#define CPU_MODEL_NAME "m68020"

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@@ -44,7 +44,16 @@ extern "C" {
* of the family.
*/
#if defined(R4650)
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define MIPS64ORION_HAS_FPU 1
#elif defined(R4650)
#define CPU_MODEL_NAME "R4650"
#define MIPS64ORION_HAS_FPU 1

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@@ -34,7 +34,16 @@ extern "C" {
* to.
*/
#if defined(no_cpu)
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define NOCPU_HAS_FPU 1
#elif defined(no_cpu)
#define CPU_MODEL_NAME "no_cpu_model"
#define NOCPU_HAS_FPU 1

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@@ -94,7 +94,28 @@ extern "C" {
#define PPC_LOW_POWER_MODE_NONE 0
#define PPC_LOW_POWER_MODE_STANDARD 1
#if defined(ppc403)
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define PPC_ALIGNMENT 4
#define PPC_CACHE_ALIGNMENT 16
#define PPC_HAS_RFCI 1
#define PPC_HAS_FPU 0
#define PPC_USE_MULTIPLE 1
#define PPC_I_CACHE 2048
#define PPC_D_CACHE 1024
#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
#define PPC_HAS_EXCEPTION_PREFIX 0
#define PPC_HAS_EVPR 0
#define PPC_INTERRUPT_MAX 16
#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
#define PPC_HAS_DOUBLE 0
#elif defined(ppc403)
/*
* IBM 403
*

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@@ -39,7 +39,17 @@ extern "C" {
* dependent features are present in a particular member of the family.
*/
#if defined(sh7032)
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define SH_HAS_FPU 0
#define SH_HAS_SEPARATE_STACKS 1
#elif defined(sh7032)
#define CPU_MODEL_NAME "SH7032"
#define SH_HAS_FPU 0

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@@ -54,7 +54,19 @@ extern "C" {
*
*/
#if defined(erc32)
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define SPARC_HAS_FPU 1
#define SPARC_HAS_BITSCAN 0
#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
#define SPARC_HAS_LOW_POWER_MODE 1
#elif defined(erc32)
#define CPU_MODEL_NAME "erc32"
#define SPARC_HAS_FPU 1

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@@ -29,7 +29,15 @@ extern "C" {
* of the family.
*/
#if defined(hpux)
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#elif defined(hpux)
#define CPU_MODEL_NAME "HP-UX"