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bsp/altera-cyclone-v: Enable FIQ for group 0 irqs

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This commit is contained in:
Sebastian Huber
2019-02-28 11:21:40 +01:00
parent 76918e180a
commit a3db5001e5
1 changed files with 4 additions and 2 deletions
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6
bsps/arm/altera-cyclone-v/include/bsp.h
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@@ -39,18 +39,20 @@ extern "C" {
#define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000
#define BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
#define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 )
#define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 )
#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
#ifndef BSP_ARM_A9MPCORE_PERIPHCLK
extern uint32_t altera_cyclone_v_a9mpcore_periphclk;
#define BSP_ARM_A9MPCORE_PERIPHCLK altera_cyclone_v_a9mpcore_periphclk
#define ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK
#endif
#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
#define BSP_ARM_L2C_310_BASE 0xfffef000
#define BSP_ARM_L2C_310_ID 0x410000c9