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bsps/mips: Delete unused files

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The MIPS port defines CPU_SIMPLE_VECTORED_INTERRUPTS to FALSE.
This commit is contained in:
Sebastian Huber
2014-04-29 09:39:08 +02:00
parent 0b344f3451
commit a16af0b367
15 changed files with 0 additions and 705 deletions
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170
c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c
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@@ -1,170 +0,0 @@
/*
* Au1x00 Interrupt Vectoring
*
* Copyright (c) 2005 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <stdlib.h>
#include <libcpu/au1x00.h>
static void call_vectored_isr(CPU_Interrupt_frame *, uint32_t , void *);
#define CALL_ISR(_vector,_frame) \
do { \
if ( _ISR_Vector_table[_vector] ) \
(_ISR_Vector_table[_vector])(_vector,_frame); \
else \
mips_default_isr(_vector); \
} while (0)
#include <rtems/bspIo.h> /* for printk */
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
cause &= (sr & SR_IMASK);
cause >>= CAUSE_IPSHIFT;
/* count/compare interrupt */
if ( cause & 0x80 ) {
unsigned long zero = 0;
/*
* I don't see a good way to disable the compare
* interrupt, so let's just ignore it.
*/
__asm__ volatile ("mtc0 %0, $11\n" :: "r" (zero));
/* CALL_ISR( AU1X00_IRQ_CNT, frame ); */
}
/* Performance counter */
if ( cause & 0x40 ) {
CALL_ISR( AU1X00_IRQ_PERF, frame );
}
/* Interrupt controller 0 */
if ( cause & 0x0c ) {
call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR);
}
/* Interrupt controller 1 */
if ( cause & 0x30 ) {
call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR);
}
/* SW[0] */
if ( cause & 0x01 )
CALL_ISR( AU1X00_IRQ_SW0, frame );
/* SW[1] */
if ( cause & 0x02 )
CALL_ISR( AU1X00_IRQ_SW1, frame );
}
void mips_default_isr( int vector )
{
unsigned int sr;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
vector, cause, sr );
rtems_fatal_error_occurred(1);
}
static void call_vectored_isr(
CPU_Interrupt_frame *frame,
uint32_t cause,
void *ctrlr
)
{
uint32_t src;
uint32_t mask;
int index;
/* get mask register */
mask = AU1X00_IC_MASKRD(ctrlr);
/* check request 0 */
src = AU1X00_IC_REQ0INT(ctrlr);
src = src & mask;
index = 0;
while (src) {
/* check LSB */
if (src & 1) {
/* clear rising/falling edge detects */
AU1X00_IC_RISINGCLR(ctrlr) = (1 << index);
AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index);
au_sync();
CALL_ISR(AU1X00_IRQ_IC0_BASE + index, frame);
}
index ++;
/* shift, and make sure MSB is clear */
src = (src >> 1) & 0x7fffffff;
}
/* check request 1 */
src = AU1X00_IC_REQ1INT(ctrlr);
src = src & mask;
index = 0;
while (src) {
/* check LSB */
if (src & 1) {
/* clear rising/falling edge detects */
AU1X00_IC_RISINGCLR(ctrlr) = (1 << index);
AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index);
au_sync();
CALL_ISR(AU1X00_IRQ_IC0_BASE + index, frame);
}
index ++;
/* shift, and make sure MSB is clear */
src = (src >> 1) & 0x7fffffff;
}
}
/* Generate a software interrupt */
int assert_sw_irq(uint32_t irqnum)
{
uint32_t cause;
if (irqnum <= 1) {
mips_get_cause(cause);
cause = cause | ((irqnum + 1) << CAUSE_IPSHIFT);
mips_set_cause(cause);
return irqnum;
} else {
return -1;
}
}
/* Clear a software interrupt */
int negate_sw_irq(uint32_t irqnum)
{
uint32_t cause;
if (irqnum <= 1) {
mips_get_cause(cause);
cause = cause & ~((irqnum + 1) << CAUSE_IPSHIFT);
mips_set_cause(cause);
return irqnum;
} else {
return -1;
}
}

262
c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
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@@ -1,262 +0,0 @@
/*
* ISR Vectoring support for the Synova Mongoose-V.
*
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <stdlib.h>
#include <libcpu/mongoose-v.h>
#include <rtems/mips/iregdef.h>
#include <rtems/mips/idtcpu.h>
#include <rtems/bspIo.h> /* for printk */
int mips_default_isr( int vector )
{
unsigned int sr, sr2;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
sr2 = sr & ~0xffff;
mips_set_sr(sr2);
printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr );
rtems_fatal_error_occurred(1);
return 0;
}
/* userspace routine to assert either software interrupt */
int assertSoftwareInterrupt( uint32_t n )
{
if( n<2 )
{
uint32_t c;
mips_get_cause(c);
c = ((n+1) << CAUSE_IPSHIFT);
mips_set_cause(c);
return n;
}
else return -1;
}
#define CALL_ISR(_vector,_frame) \
do { \
if( _ISR_Vector_table[_vector] ) \
(_ISR_Vector_table[_vector])(_vector,_frame); \
else \
mips_default_isr(_vector); \
} while (0)
/*
* Instrumentation tweaks for isr timing measurement, turning them off
* via this #if will remove the code entirely from the RTEMS kernel.
*/
#if 0
#define SET_ISR_FLAG( offset ) *((uint32_t*)(0x8001e000+offset)) = 1;
#define CLR_ISR_FLAG( offset ) *((uint32_t*)(0x8001e000+offset)) = 0;
#else
#define SET_ISR_FLAG( offset )
#define CLR_ISR_FLAG( offset )
#endif
static volatile uint32_t _ivcause, _ivsr;
static uint32_t READ_CAUSE(void)
{
mips_get_cause( _ivcause );
_ivcause &= SR_IMASK; /* mask off everything other than the interrupt bits */
return ((_ivcause & (_ivsr & SR_IMASK)) >> CAUSE_IPSHIFT);
}
/*
* This rather strangely coded routine enforces an interrupt priority
* scheme. As it runs thru finding whichever interrupt caused it to get
* here, it test for other interrupts arriving in the meantime (maybe it
* occured while the vector code is executing for instance). Each new
* interrupt will be served in order of its priority. In an effort to
* minimize overhead, the cause register is only fetched after an
* interrupt is serviced. Because of the intvect goto's, this routine
* will only exit when all interrupts have been serviced and no more
* have arrived, this improves interrupt latency at the cost of
* increasing scheduling jitter; though scheduling jitter should only
* become apparent in high interrupt load conditions.
*/
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
uint32_t cshifted;
/* mips_get_sr( sr ); */
_ivsr = frame->c0_sr;
cshifted = READ_CAUSE();
intvect:
if( cshifted & 0x3 )
{
/* making the software interrupt the highest priority is kind of
* stupid, but it makes the bit testing lots easier. On the other
* hand, these ints are infrequently used and the testing overhead
* is minimal. Who knows, high-priority software ints might be
* handy in some situation.
*/
/* unset both software int cause bits */
mips_set_cause( _ivcause & ~(3 << CAUSE_IPSHIFT) );
if ( cshifted & 0x01 ) /* SW[0] */
{
CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame );
}
if ( cshifted & 0x02 ) /* SW[1] */
{
CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame );
}
cshifted = READ_CAUSE();
}
if ( cshifted & 0x04 ) /* IP[0] ==> INT0 == TIMER1 */
{
SET_ISR_FLAG( 0x4 );
CALL_ISR( MONGOOSEV_IRQ_TIMER1, frame );
CLR_ISR_FLAG( 0x4 );
if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect;
}
if ( cshifted & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/
{
SET_ISR_FLAG( 0x8 );
CALL_ISR( MONGOOSEV_IRQ_TIMER2, frame );
CLR_ISR_FLAG( 0x8 );
if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect;
}
if ( cshifted & 0x10 ) /* IP[2] ==> INT2 */
{
SET_ISR_FLAG( 0x10 );
CALL_ISR( MONGOOSEV_IRQ_INT2, frame );
CLR_ISR_FLAG( 0x10 );
if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect;
}
if ( cshifted & 0x20 ) /* IP[3] ==> INT3 == FPU interrupt */
{
SET_ISR_FLAG( 0x20 );
CALL_ISR( MONGOOSEV_IRQ_INT3, frame );
CLR_ISR_FLAG( 0x20 );
if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect;
}
if ( cshifted & 0x40 ) /* IP[4] ==> INT4, external interrupt */
{
SET_ISR_FLAG( 0x40 );
CALL_ISR( MONGOOSEV_IRQ_INT4, frame );
CLR_ISR_FLAG( 0x40 );
if( (cshifted = READ_CAUSE()) & 0x3f ) goto intvect;
}
if ( cshifted & 0x80 ) /* IP[5] ==> INT5, peripheral interrupt */
{
uint32_t bit;
uint32_t pf_icr, pf_mask, pf_reset = 0;
uint32_t i, m;
pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER );
/*
for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 )
{
if ( pf_icr & pf_mask )
{
SET_ISR_FLAG( 0x80 + (bit*4) );
CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit, frame );
CLR_ISR_FLAG( 0x80 + (bit*4) );
pf_reset |= pf_mask;
if( (cshifted = READ_CAUSE()) & 0xff ) break;
}
}
*/
/*
* iterate thru 32 bits in 4 chunks of 8 bits each. This lets us
* quickly get past unasserted interrupts instead of flogging our
* way thru a full 32 bits. pf_mask shifts left 8 bits at a time
* to serve as a interrupt cause test mask.
*/
for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) )
{
if ( pf_icr & pf_mask )
{
/* one or more of the 8 bits we're testing is high */
m = (1 << bit);
/* iterate thru the 8 bits, servicing any of the interrupts */
for(i=0; (i<8 && pf_icr); (i++, m <<= 1))
{
if( pf_icr & m )
{
SET_ISR_FLAG( 0x80 + ((bit + i) * 4) );
CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit + i, frame );
CLR_ISR_FLAG( 0x80 + ((bit + i) * 4) );
/* or each serviced interrupt into our interrupt clear mask */
pf_reset |= m;
/* xor off each int we service so we can immediately
* exit once we get the last one
*/
pf_icr %= m;
/* if another interrupt has arrived, jump out right
* away but be sure to reset all the interrupts we've
* already serviced
*/
if( READ_CAUSE() & 0xff ) goto pfexit;
}
}
}
}
pfexit:
MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, pf_reset );
}
/*
* this is a last ditch interrupt check, if an interrupt arrives
* after this step, servicing it will incur the entire interrupt
* overhead cost.
*/
if( (cshifted = READ_CAUSE()) & 0xff ) goto intvect;
}

49
c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c
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@@ -1,49 +0,0 @@
#include <rtems.h>
#include <stdlib.h>
void mips_default_isr( int vector );
#define CALL_ISR(_vector,_frame) \
do { \
if ( _ISR_Vector_table[_vector] ) \
(_ISR_Vector_table[_vector])(_vector,_frame); \
else \
mips_default_isr(_vector); \
} while (0)
#include <rtems/bspIo.h> /* for printk */
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
unsigned int i;
unsigned int mask;
mips_get_sr( sr );
mips_get_cause( cause );
cause &= (sr & SR_IMASK);
cause >>= CAUSE_IPSHIFT;
/* XXX check this and think about it. */
for ( i=1, mask=0x80 ; i<=8 ; i++, mask >>= 1 ) {
if ( cause & mask )
CALL_ISR( MIPS_EXCEPTION_BASE + 8 - i, frame );
}
}
void mips_default_isr( int vector )
{
unsigned int sr;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
vector, cause, sr );
rtems_fatal_error_occurred(1);
}

54
c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c
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@@ -1,54 +0,0 @@
/*
* RM5231 Interrupt Vectoring
*
* vectorisrs.c,v 1.6 2004/06/23 18:16:36
*/
#include <rtems.h>
#include <stdlib.h>
#include <libcpu/rm5231.h>
void mips_default_isr( int vector );
#define CALL_ISR(_vector,_frame) \
do { \
if ( _ISR_Vector_table[_vector] ) \
(_ISR_Vector_table[_vector])(_vector,_frame); \
else \
mips_default_isr(_vector); \
} while (0)
#include <rtems/bspIo.h> /* for printk */
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
unsigned int i;
unsigned int mask;
mips_get_sr( sr );
mips_get_cause( cause );
cause &= (sr & SR_IMASK);
cause >>= CAUSE_IPSHIFT;
for ( i=1, mask=0x80 ; i<=8 ; i++, mask >>= 1 ) {
if ( cause & mask )
CALL_ISR( MIPS_INTERRUPT_BASE + 8 - i, frame );
}
}
void mips_default_isr( int vector )
{
unsigned int sr;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
vector, cause, sr );
rtems_fatal_error_occurred(1);
}

58
c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
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@@ -1,58 +0,0 @@
/*
* TX3904 Interrupt Vectoring
*/
#include <rtems.h>
#include <stdlib.h>
#include <libcpu/tx3904.h>
void mips_default_isr( int vector );
#define CALL_ISR(_vector,_frame) \
do { \
if ( _ISR_Vector_table[_vector] ) \
(_ISR_Vector_table[_vector])(_vector,_frame); \
else \
mips_default_isr(_vector); \
} while (0)
#include <rtems/bspIo.h> /* for printk */
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
cause &= (sr & SR_IMASK);
cause >>= CAUSE_IPSHIFT;
if ( cause & 0x80 ) /* IP[5] ==> INT0 */
CALL_ISR( TX3904_IRQ_INT0, frame );
if ( cause & 0x40 ) { /* (IP[4] == 1) ==> IP[0-3] are valid */
unsigned int v = (cause >> 2) & 0x0f;
CALL_ISR( MIPS_INTERRUPT_BASE + v, frame );
}
if ( cause & 0x02 ) /* SW[0] */
CALL_ISR( TX3904_IRQ_SOFTWARE_1, frame );
if ( cause & 0x01 ) /* IP[1] */
CALL_ISR( TX3904_IRQ_SOFTWARE_2, frame );
}
void mips_default_isr( int vector )
{
unsigned int sr;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
vector, cause, sr );
rtems_fatal_error_occurred(1);
}

61
c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c
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@@ -1,61 +0,0 @@
/*
* TX4925 Interrupt Vectoring
*
* vectorisrs.c,v 1.6 2004/06/23 18:16:36
*/
#include <rtems.h>
#include <stdlib.h>
#include <libcpu/tx4925.h>
void mips_default_isr( int vector );
#define CALL_ISR(_vector,_frame) \
do { \
if ( _ISR_Vector_table[_vector] ) \
(_ISR_Vector_table[_vector])(_vector,_frame); \
else \
mips_default_isr(_vector); \
} while (0)
#include <rtems/bspIo.h> /* for printk */
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
unsigned int pending;
mips_get_sr( sr );
mips_get_cause( cause );
pending = (cause & sr & 0x700) >> CAUSE_IPSHIFT;
if ( pending & 0x4 ) { /* (IP[2] == 1) ==> IP[3-7] are valid */
unsigned int v = (cause >> (CAUSE_IPSHIFT + 3)) & 0x1f;
CALL_ISR( MIPS_INTERRUPT_BASE + v, frame );
}
if ( pending & 0x01 ) /* IP[0] */
CALL_ISR( TX4925_IRQ_SOFTWARE_1, frame );
if ( pending & 0x02 ) /* IP[1] */
CALL_ISR( TX4925_IRQ_SOFTWARE_2, frame );
}
void mips_default_isr( int vector )
{
unsigned int sr;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
vector, cause, sr );
while(1); /* Lock it up */
rtems_fatal_error_occurred(1);
}