forked from Imagelibrary/rtems
bsps: Move ARM GICv2 driver to bsps/shared
This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
This commit is contained in:
Kinsey Moore
committed by
Joel Sherrill
Joel Sherrill
parent
f0859573f9
commit
a151ee167e
275
bsps/shared/dev/irq/arm-gicv2.c
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275
bsps/shared/dev/irq/arm-gicv2.c
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@@ -0,0 +1,275 @@
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/*
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* Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <info@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <dev/irq/arm-gic.h>
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#include <bsp/irq.h>
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#include <bsp/irq-generic.h>
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#include <bsp/start.h>
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#define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE)
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#define PRIORITY_DEFAULT 127
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/*
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* The following variants
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*
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* - GICv1 with Security Extensions,
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* - GICv2 without Security Extensions, or
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* - within Secure processor mode
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*
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* have the ability to assign group 0 or 1 to individual interrupts. Group
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* 0 interrupts can be configured to raise an FIQ exception. This enables
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* the use of NMIs with respect to RTEMS.
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*
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* BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
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* define. Use arm_gic_irq_set_group() to change the group of an
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* interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is
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* defined).
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*/
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#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
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#define DIST_ICDDCR (GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE)
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#define CPUIF_ICCICR \
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(GIC_CPUIF_ICCICR_CBPR | GIC_CPUIF_ICCICR_FIQ_EN \
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| GIC_CPUIF_ICCICR_ACK_CTL | GIC_CPUIF_ICCICR_ENABLE_GRP_1 \
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| GIC_CPUIF_ICCICR_ENABLE)
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#else
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#define DIST_ICDDCR GIC_DIST_ICDDCR_ENABLE
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#define CPUIF_ICCICR GIC_CPUIF_ICCICR_ENABLE
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#endif
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void gicvx_interrupt_dispatch(void)
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{
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volatile gic_cpuif *cpuif = GIC_CPUIF;
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uint32_t icciar = cpuif->icciar;
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rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
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rtems_vector_number spurious = 1023;
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if (vector != spurious) {
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arm_interrupt_handler_dispatch(vector);
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cpuif->icceoir = icciar;
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}
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}
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void bsp_interrupt_vector_enable(rtems_vector_number vector)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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gic_id_enable(dist, vector);
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}
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void bsp_interrupt_vector_disable(rtems_vector_number vector)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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gic_id_disable(dist, vector);
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}
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static inline uint32_t get_id_count(volatile gic_dist *dist)
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{
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uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr);
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id_count = 32 * (id_count + 1);
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id_count = id_count <= 1020 ? id_count : 1020;
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return id_count;
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}
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static void enable_fiq(void)
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{
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#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
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rtems_interrupt_level level;
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rtems_interrupt_local_disable(level);
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level &= ~ARM_PSR_F;
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rtems_interrupt_local_enable(level);
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#endif
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}
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rtems_status_code bsp_interrupt_facility_initialize(void)
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{
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volatile gic_cpuif *cpuif = GIC_CPUIF;
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volatile gic_dist *dist = ARM_GIC_DIST;
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uint32_t id_count = get_id_count(dist);
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uint32_t id;
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arm_interrupt_facility_set_exception_handler();
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for (id = 0; id < id_count; id += 32) {
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#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
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dist->icdigr[id / 32] = 0xffffffff;
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#endif
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dist->icdicer[id / 32] = 0xffffffff;
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}
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for (id = 0; id < id_count; ++id) {
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gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
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}
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for (id = 32; id < id_count; ++id) {
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gic_id_set_targets(dist, id, 0x01);
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}
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cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
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cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
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cpuif->iccicr = CPUIF_ICCICR;
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dist->icddcr = GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE;
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enable_fiq();
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return RTEMS_SUCCESSFUL;
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}
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#ifdef RTEMS_SMP
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BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
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{
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volatile gic_cpuif *cpuif = GIC_CPUIF;
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volatile gic_dist *dist = ARM_GIC_DIST;
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uint32_t id;
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while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) {
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/* Wait */
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}
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#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
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dist->icdigr[0] = 0xffffffff;
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#endif
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/* Initialize Peripheral Private Interrupts (PPIs) */
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for (id = 0; id < 32; ++id) {
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gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
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}
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cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
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cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
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cpuif->iccicr = CPUIF_ICCICR;
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enable_fiq();
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}
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#endif
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rtems_status_code arm_gic_irq_set_priority(
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rtems_vector_number vector,
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uint8_t priority
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)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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if (bsp_interrupt_is_valid_vector(vector)) {
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volatile gic_dist *dist = ARM_GIC_DIST;
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gic_id_set_priority(dist, vector, priority);
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} else {
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sc = RTEMS_INVALID_ID;
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}
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return sc;
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}
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rtems_status_code arm_gic_irq_get_priority(
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rtems_vector_number vector,
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uint8_t *priority
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)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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if (bsp_interrupt_is_valid_vector(vector)) {
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volatile gic_dist *dist = ARM_GIC_DIST;
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*priority = gic_id_get_priority(dist, vector);
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} else {
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sc = RTEMS_INVALID_ID;
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}
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return sc;
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}
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rtems_status_code arm_gic_irq_set_group(
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rtems_vector_number vector,
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gic_group group
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)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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if (bsp_interrupt_is_valid_vector(vector)) {
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volatile gic_dist *dist = ARM_GIC_DIST;
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gic_id_set_group(dist, vector, group);
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} else {
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sc = RTEMS_INVALID_ID;
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}
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return sc;
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}
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rtems_status_code arm_gic_irq_get_group(
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rtems_vector_number vector,
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gic_group *group
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)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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if (bsp_interrupt_is_valid_vector(vector)) {
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volatile gic_dist *dist = ARM_GIC_DIST;
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*group = gic_id_get_group(dist, vector);
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} else {
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sc = RTEMS_INVALID_ID;
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}
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return sc;
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}
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void bsp_interrupt_set_affinity(
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rtems_vector_number vector,
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const Processor_mask *affinity
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)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0);
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gic_id_set_targets(dist, vector, targets);
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}
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void bsp_interrupt_get_affinity(
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rtems_vector_number vector,
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Processor_mask *affinity
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)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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uint8_t targets = gic_id_get_targets(dist, vector);
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_Processor_mask_From_uint32_t(affinity, targets, 0);
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}
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void arm_gic_trigger_sgi(
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rtems_vector_number vector,
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arm_gic_irq_software_irq_target_filter filter,
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uint8_t targets
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)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter)
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| GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets)
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#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
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| GIC_DIST_ICDSGIR_NSATT
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#endif
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| GIC_DIST_ICDSGIR_SGIINTID(vector);
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}
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@@ -134,7 +134,7 @@
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#define ARM_GIC_REDIST ((volatile gic_redist *) BSP_ARM_GIC_REDIST_BASE)
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#define ARM_GIC_SGI_PPI (((volatile gic_sgi_ppi *) ((char*)BSP_ARM_GIC_REDIST_BASE + (1 << 16))))
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void gicv3_interrupt_dispatch(void)
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void gicvx_interrupt_dispatch(void)
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{
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uint32_t icciar = READ_SR(ICC_IAR1);
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rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
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