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bsp/mpc8260: Move libcpu content to bsps

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This patch is a part of the BSP source reorganization.

Update #3285.
This commit is contained in:
Sebastian Huber
2018-03-23 16:04:18 +01:00
parent 0cab067f1c
commit a12dcff877
8 changed files with 5 additions and 45 deletions
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9
c/src/lib/libbsp/powerpc/mpc8260ads/Makefile.am
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@@ -56,10 +56,11 @@ endif
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/ppc-dec-timer.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/mpc8260/console-generic.rel \
../../../libcpu/@RTEMS_CPU@/mpc8260/cpm.rel \
../../../libcpu/@RTEMS_CPU@/mpc8260/mmu.rel
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/mpc8260ads/dev/console-generic.c
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/mpc8260ads/start/brg.c
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/mpc8260ads/start/cp.c
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/mpc8260ads/start/dpram.c
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/mpc8260ads/start/mmu.c
EXTRA_DIST += times

24
c/src/lib/libcpu/powerpc/Makefile.am
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@@ -106,28 +106,4 @@ mpc8xx_mmu_rel_CPPFLAGS = $(AM_CPPFLAGS)
mpc8xx_mmu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
EXTRA_DIST += mpc8260/README
if mpc8260
# mpc8260/console-generic
noinst_PROGRAMS += mpc8260/console-generic.rel
mpc8260_console_generic_rel_SOURCES = mpc8260/console-generic/console-generic.c \
mpc8260/include/console.h
mpc8260_console_generic_rel_CPPFLAGS = $(AM_CPPFLAGS)
mpc8260_console_generic_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
# mpc8260/cpm
noinst_PROGRAMS += mpc8260/cpm.rel
mpc8260_cpm_rel_SOURCES = mpc8260/cpm/cp.c mpc8260/cpm/dpram.c mpc8260/cpm/brg.c \
mpc8260/include/cpm.h
mpc8260_cpm_rel_CPPFLAGS = $(AM_CPPFLAGS)
mpc8260_cpm_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
# mpc8260/mmu
noinst_PROGRAMS += mpc8260/mmu.rel
mpc8260_mmu_rel_SOURCES = mpc8260/mmu/mmu.c \
mpc8260/include/mmu.h
mpc8260_mmu_rel_CPPFLAGS = $(AM_CPPFLAGS)
mpc8260_mmu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
include $(top_srcdir)/../../../automake/local.am

17
c/src/lib/libcpu/powerpc/mpc8260/README
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@@ -1,17 +0,0 @@
# Modified from mpc860 version by A. Dachs, 28-4-00
Various non BSP dependant support routines.
clock - Uses the MPC8260 decrementer to
generate RTEMS clock ticks.
console_generic - Uses the MPC8260 SCCs and SMCs to to serial I/O
include - console.h: function declarations for console related functions
timer - Uses the MPC8260 timebase register for timing
tests. It only uses the lower 32 bits
vectors - MPC8260 specific vector entry points.
Includes CPU dependant, application independant
handlers: alignment.

1096
c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c
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File diff suppressed because it is too large Load Diff

198
c/src/lib/libcpu/powerpc/mpc8260/cpm/brg.c
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@@ -1,198 +0,0 @@
/*
* Baud rate generator management functions.
*
* This file contains routines for allocating baud rate generators
* and clock sources to the SCCs and FCCs on the MPC8260. The
* allocation is a little more complex on this processor because
* there are restrictions on which brgs and clks can be assigned to
* a particular port. Rather than coming up with a fixed assignment
* these routines try to allocate resources sensibly.
*
* *** All attempts to allocate a BRG or CLK line should be made via
* calls to these routines or they simply won't work.
*/
/*
* Author: Andy Dachs <a.dachs@sstl.co.uk>
* Copyright Surrey Satellite Technology Limited (SSTL), 2001
*
* Derived in part from work by:
*
* Author: Jay Monkman (jmonkman@frasca.com)
* Copyright (C) 1998 by Frasca International, Inc.
* and
* W. Eric Norum
* Saskatchewan Accelerator Laboratory
* University of Saskatchewan
* Saskatoon, Saskatchewan, CANADA
* eric@skatter.usask.ca
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <mpc8260.h>
#include <mpc8260/cpm.h>
#include <rtems/bspIo.h>
#define NUM_BRGS 8
#define NUM_CLKS 20
/* Used to track the usage of the baud rate generators */
/* (initialised to zeros) */
static unsigned long brg_spd[NUM_BRGS];
static unsigned int brg_use_count[NUM_BRGS];
/* Used to track the usage of the clock inputs */
/* (initialised to zeros) */
static unsigned int clk_use_count[NUM_BRGS];
/*
* Compute baud-rate-generator configuration register value
*/
int
m8xx_get_brg_cd (int baud)
{
int divisor;
int div16 = 0;
divisor = ((bsp_serial_per_sec) + (baud / 2)) / baud;
if (divisor > 4096) {
div16 = 1;
divisor = (divisor + 8) / 16;
}
return M8260_BRG_EN | M8260_BRG_EXTC_BRGCLK |
((divisor - 1) << 1) | div16;
}
/*
* Allocates an existing brg if one is already programmed for the same
* baud rate. Otherwise a new brg is assigned
* AFD: on the mpc8260 only some combinations of SCC/SMC and BRG are allowed
* so add a mask which specifies which of the BRGs we can choose from
*/
int
m8xx_get_brg(unsigned brgmask, int baud)
{
int i;
/* first try to find a BRG that is already at the right speed */
for ( i = 0; i < NUM_BRGS; i++ ) {
if ( (1 << i) & brgmask ) /* is this brg allowed? */
if ( brg_spd[i] == baud ) {
break;
}
}
if ( i == NUM_BRGS ) { /* I guess we didn't find one */
for ( i = 0; i < NUM_BRGS; i++ ) {
if (((1<<i) & brgmask) && (brg_use_count[i] == 0)) {
break;
}
}
}
if (i != NUM_BRGS) {
brg_use_count[i]++;
brg_spd[i]=baud;
switch (i) {
case 0:
m8260.brgc1 = M8260_BRG_RST;
m8260.brgc1 = m8xx_get_brg_cd(baud);
break;
case 1:
m8260.brgc2 = M8260_BRG_RST;
m8260.brgc2 = m8xx_get_brg_cd(baud);
break;
case 2:
m8260.brgc3 = M8260_BRG_RST;
m8260.brgc3 = m8xx_get_brg_cd(baud);
break;
case 3:
m8260.brgc4 = M8260_BRG_RST;
m8260.brgc4 = m8xx_get_brg_cd(baud);
break;
case 4:
m8260.brgc5 = M8260_BRG_RST;
m8260.brgc5 = m8xx_get_brg_cd(baud);
break;
case 5:
m8260.brgc6 = M8260_BRG_RST;
m8260.brgc6 = m8xx_get_brg_cd(baud);
break;
case 6:
m8260.brgc7 = M8260_BRG_RST;
m8260.brgc7 = m8xx_get_brg_cd(baud);
break;
case 7:
m8260.brgc8 = M8260_BRG_RST;
m8260.brgc8 = m8xx_get_brg_cd(baud);
break;
}
return i;
}
else {
printk( "Could not assign a brg for %d\n", baud );
return -1;
}
}
/*
* When the brg is no longer needed call this routine to free the
* resource for re--use.
*/
void
m8xx_free_brg( int brg_num )
{
if ( (brg_num>=0) && (brg_num<NUM_BRGS) )
if (brg_use_count[brg_num] > 0 )
brg_use_count[brg_num]--;
}
#ifdef DEBUG_BRG
static void m8xx_dump_brgs( void )
{
int i;
for (i=0; i<NUM_BRGS; i++ )
printk( "Brg[%d]: %d %d\n", i, brg_use_count[i], brg_spd[i] );
}
#endif
/*
* Reserve one of a range of clock inputs
*/
int
m8xx_get_clk( unsigned clkmask )
{
int i;
for ( i = 0; i < NUM_CLKS; i++ ) {
if (((1<<i) & clkmask) && (clk_use_count[i] == 0)) {
break;
}
}
if (i != NUM_CLKS) {
clk_use_count[i]++;
return i;
} else {
printk( "Could not assign clock in the range %X\n", clkmask );
return -1;
}
}
/*
* When the clock is no longer needed call this routine to free the
* resource for re--use.
*/
void
m8xx_free_clk( int clk_num )
{
if ( (clk_num>=0) && (clk_num<NUM_BRGS) )
if (clk_use_count[clk_num] > 0 )
clk_use_count[clk_num]--;
}

34
c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c
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@@ -1,34 +0,0 @@
/*
* cp.c
*
* MPC8xx CPM RISC Communication Processor routines.
*
* Based on code (alloc860.c in eth_comm port) by
* Jay Monkman (jmonkman@frasca.com),
* which, in turn, is based on code by
* W. Eric Norum (eric@skatter.usask.ca).
*
* Modifications by Darlene Stewart (Darlene.Stewart@iit.nrc.ca):
* Copyright (c) 1999, National Research Council of Canada
*/
#include <rtems.h>
#include <mpc8260.h>
#include <mpc8260/cpm.h>
/*
* Send a command to the CPM RISC processer
*/
void m8xx_cp_execute_cmd( uint32_t command )
{
uint16_t lvl;
rtems_interrupt_disable(lvl);
while (m8260.cpcr & M8260_CR_FLG) {
continue;
}
m8260.cpcr = command | M8260_CR_FLG;
rtems_interrupt_enable (lvl);
}

93
c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c
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@@ -1,93 +0,0 @@
/*
* dpram.c
*
* MPC8260 dual-port RAM allocation routines
*
* Based on code in mpc8xx which is
* Based on code (alloc860.c in eth_comm port) by
* Jay Monkman (jmonkman@frasca.com),
* which, in turn, is based on code by
* W. Eric Norum (eric@skatter.usask.ca).
*
*
* Modifications :
* Copyright (c) 1999, National Research Council of Canada
*
* MPC8260 modifications Andy Dachs, <a.dachs@sstl.co.uk>
* Surrey Satellite Technology Limited, 2001
*/
#include <rtems.h>
#include <rtems/error.h>
#include <mpc8260.h>
#include <mpc8260/cpm.h>
/*
* Allocation order:
* - Dual-Port RAM section 0
* - Dual-Port RAM section 1
* - Dual-Port RAM section 2
* - Dual-Port RAM section 3
*/
static struct {
uint8_t *base;
size_t size;
unsigned int used;
} dpram_regions[] = {
/* { (uint8_t *)&m8260.dpram0[0], sizeof m8260.dpram0, 0 },*/
{ (uint8_t *)&m8260.dpram1[0], sizeof m8260.dpram1, 0 },
/* { (uint8_t *)&m8260.dpram2[0], sizeof m8260.dpram2, 0 },*/
{ (uint8_t *)&m8260.dpram3[0], sizeof m8260.dpram3, 0 }
};
#define NUM_DPRAM_REGIONS (sizeof(dpram_regions) / sizeof(dpram_regions[0]))
void *
m8xx_dpram_allocate( unsigned int byte_count )
{
unsigned int i;
ISR_Level level;
void *blockp = NULL;
byte_count = (byte_count + 3) & ~0x3;
/*
* Running with interrupts disabled is usually considered bad
* form, but this routine is probably being run as part of an
* initialization sequence so the effect shouldn't be too severe.
*/
_ISR_Local_disable (level);
for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) {
/*
* Verify that the region is available for use.
* This test is necessary because if extra microcode modules
* are installed, some regions are locked and unavailable.
* See MPC860 User's Manual Pages 19-9 to 19-11.
*/
if (dpram_regions[i].used == 0) {
volatile unsigned char *cp = dpram_regions[i].base;
*cp = 0xAA;
if (*cp != 0xAA)
dpram_regions[i].used = dpram_regions[i].size;
else {
*cp = 0x55;
if (*cp != 0x55)
dpram_regions[i].used = dpram_regions[i].size;
}
*cp = 0x0;
}
if (dpram_regions[i].size - dpram_regions[i].used >= byte_count) {
blockp = dpram_regions[i].base + dpram_regions[i].used;
dpram_regions[i].used += byte_count;
break;
}
}
_ISR_Local_enable(level);
if (blockp == NULL)
rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count);
return blockp;
}

130
c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c
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@@ -1,130 +0,0 @@
/*
* mmu.c
*
* This file contains routines for initializing
* and manipulating the MMU on the MPC8xx.
*
* Copyright (c) 1999, National Research Council of Canada
*
* Trivially modified for mpc8260 21.3.2001
* Andy Dachs <a.dachs@sstl.co.uk>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <mpc8260.h>
#include <mpc8260/mmu.h>
/*
* mmu_init
*
* This routine sets up the virtual memory maps on an MPC8xx.
* The MPC8xx does not support block address translation (BATs)
* and does not have segment registers. Thus, we must set up page
* translation. However, its MMU supports variable size pages
* (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task.
*
* The MPC8xx has separate data and instruction 32-entry translation
* lookaside buffers (TLB). By mapping all of DRAM as one huge page,
* we can preload the TLBs and not have to be concerned with taking
* TLB miss exceptions.
*
* We set up the virtual memory map so that virtual address of a
* location is equal to its real address.
*/
void mmu_init( void )
{
#if 0
/* so far we leave mmu uninitialised */
register uint32_t reg1, i;
/*
* Initialize the TLBs
*
* Instruction address translation and data address translation
* must be disabled during initialization (IR=0, DR=0 in MSR).
* We can assume the MSR has already been set this way.
*/
/*
* Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR)
* GPM [0] 0b0 = PowerPC mode
* PPM [1] 0b0 = Page resolution of protection
* CIDEF [2] 0b0/0b1 = Default cache-inhibit attribute =
* NO for IMMU, YES for DMMU!
* reserved/WTDEF [3] 0b0 = Default write-through attribute = not
* RSV4x [4] 0b0 = 4 entries not reserved
* reserved/TWAM [5] 0b0/0b1 = 4-Kbyte page hardware assist
* PPCS [6] 0b0 = Ignore user/supervisor state
* reserved [7-18] 0x00
* xTLB_INDX [19-23] 31 = 0x1F
* reserved [24-31] 0x00
*
* Note: It is important that cache-inhibit be set as the default for the
* data cache when the DMMU is disabled in order to prevent internal memory
* mapped registers from being cached accidentally when address translation
* is turned off at the start of exception processing.
*/
reg1 = M8xx_MI_CTR_ITLB_INDX(31);
_mtspr( M8xx_MI_CTR, reg1 );
reg1 = M8xx_MD_CTR_CIDEF | M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31);
_mtspr( M8xx_MD_CTR, reg1 );
_isync;
/*
* Invalidate all TLB entries in both TLBs.
* Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so
* all 32 entries are invalidated.
*/
__asm__ volatile ("tlbia\n"::);
_isync;
/*
* Set Current Address Space ID Register (M_CASID).
* Supervisor: CASID = 0
*/
reg1 = 0;
_mtspr( M8xx_M_CASID, reg1 );
/*
* Initialize the MMU Access Protection Registers (MI_AP, MD_AP)
* We ignore the Access Protection Group (APG) mechanism globally
* by setting all of the Mx_AP fields to 0b01 : client access
* permission is defined by page protection bits.
*/
reg1 = 0x55555555;
_mtspr( M8xx_MI_AP, reg1 );
_mtspr( M8xx_MD_AP, reg1 );
/*
* Load both 32-entry TLBs with values from the MMU_TLB_table
* which is defined in the BSP.
* Note the _TLB_Table must have at most 32 entries. This code
* makes no effort to enforce this restriction.
*/
for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) {
reg1 = MMU_TLB_table[i].mmu_epn;
_mtspr( M8xx_MI_EPN, reg1 );
_mtspr( M8xx_MD_EPN, reg1 );
reg1 = MMU_TLB_table[i].mmu_twc;
_mtspr( M8xx_MI_TWC, reg1 );
_mtspr( M8xx_MD_TWC, reg1 );
reg1 = MMU_TLB_table[i].mmu_rpn; /* RPN must be written last! */
_mtspr( M8xx_MI_RPN, reg1 );
_mtspr( M8xx_MD_RPN, reg1 );
}
/*
* Turn on address translation by setting MSR[IR] and MSR[DR].
*/
_CPU_MSR_GET( reg1 );
reg1 |= PPC_MSR_IR | PPC_MSR_DR;
_CPU_MSR_SET( reg1 );
#endif
}