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bsps/arm: Change code to explicit selection of cache implementation for ARM BSPs.

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The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.

The ARM targets equipped by cache should include
appropriate implementation.

Next options are available for now

c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
  basic ARM cache integrated on the CPU core directly
  which requires only CP15 oparations

c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
  support for case where ARM L2C-310 cache controller
  is used. It is accessible as mmaped peripheral.

c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
  Cortex-M specific cache support

Updates #2782
Updates #2783
This commit is contained in:
Pavel Pisa
2016-07-03 17:26:50 +02:00
parent 886b962e7b
commit a114f99bd2
10 changed files with 190 additions and 124 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
c/src/lib/libbsp/arm/beagle/Makefile.am
View File

@@ -123,8 +123,9 @@ libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
###############################################################################
# Special Rules #

6
c/src/lib/libbsp/arm/csb336/Makefile.am
View File

@@ -10,6 +10,7 @@ include_HEADERS = include/bsp.h
include_HEADERS += ../../shared/include/tm27.h
include_bsp_HEADERS =
libbsp_a_CPPFLAGS =
nodist_include_HEADERS = include/bspopts.h
nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -51,8 +52,9 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
if HAS_NETWORKING
network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__

6
c/src/lib/libbsp/arm/csb337/Makefile.am
View File

@@ -13,6 +13,7 @@ include_HEADERS += include/sed1356.h
endif
include_bsp_HEADERS =
libbsp_a_CPPFLAGS =
if ENABLE_UMON
include_umondir = $(includedir)/umon
@@ -88,8 +89,9 @@ endif
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
if HAS_NETWORKING
network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__

6
c/src/lib/libbsp/arm/lpc32xx/Makefile.am
View File

@@ -145,8 +145,10 @@ libbsp_a_SOURCES += misc/idle-thread.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c

8
c/src/lib/libbsp/arm/raspberrypi/Makefile.am
View File

@@ -45,8 +45,7 @@ include_bsp_HEADERS += include/mmu.h
include_bsp_HEADERS += include/usart.h
include_bsp_HEADERS += include/raspberrypi.h
include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/cache_.h \
../../../libcpu/arm/shared/include/arm-cp15.h
include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h
###############################################################################
# Data #
@@ -125,8 +124,9 @@ libbsp_a_SOURCES += misc/timer.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c

4
c/src/lib/libbsp/arm/raspberrypi/preinstall.am
View File

@@ -130,10 +130,6 @@ $(PROJECT_INCLUDE)/bsp/raspberrypi.h: include/raspberrypi.h $(PROJECT_INCLUDE)/b
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/raspberrypi.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/raspberrypi.h
$(PROJECT_INCLUDE)/libcpu/cache_.h: ../../../libcpu/arm/shared/include/cache_.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache_.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache_.h
$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h

5
c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am
View File

@@ -125,8 +125,9 @@ libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c

134
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h Normal file
View File

@@ -0,0 +1,134 @@
/**
* @file
*
* @ingroup arm
*
* @brief ARM cache defines and implementation.
*/
/*
* Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
#define LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
#include <libcpu/arm-cp15.h>
#define CPU_DATA_CACHE_ALIGNMENT 32
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
#if defined(__ARM_ARCH_7A__)
/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */
#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
#endif
static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
{
arm_cp15_data_cache_clean_line(d_addr);
}
static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
{
arm_cp15_data_cache_invalidate_line(d_addr);
}
static inline void _CPU_cache_freeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
{
arm_cp15_instruction_cache_invalidate_line(d_addr);
}
static inline void _CPU_cache_freeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_flush_entire_data(void)
{
arm_cp15_data_cache_test_and_clean();
}
static inline void _CPU_cache_invalidate_entire_data(void)
{
arm_cp15_data_cache_invalidate();
}
static inline void _CPU_cache_enable_data(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl |= ARM_CP15_CTRL_C;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_disable_data(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
arm_cp15_data_cache_test_and_clean_and_invalidate();
ctrl = arm_cp15_get_control();
ctrl &= ~ARM_CP15_CTRL_C;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_invalidate_entire_instruction(void)
{
arm_cp15_instruction_cache_invalidate();
}
static inline void _CPU_cache_enable_instruction(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl |= ARM_CP15_CTRL_I;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_disable_instruction(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl &= ~ARM_CP15_CTRL_I;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
#endif /* LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H */

6
c/src/lib/libbsp/arm/smdk2410/Makefile.am
View File

@@ -11,6 +11,7 @@ include_HEADERS += ../gp32/smc/smc.h
include_HEADERS += ../../shared/include/tm27.h
include_bsp_HEADERS =
libbsp_a_CPPFLAGS =
nodist_include_HEADERS = include/bspopts.h
nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -57,8 +58,9 @@ libbsp_a_SOURCES += ../gp32/smc/smc.c ../gp32/smc/smc.h
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel \
../../../libcpu/@RTEMS_CPU@/s3c24xx/clock.rel \

134
c/src/lib/libcpu/arm/shared/include/cache_.h
View File

@@ -3,7 +3,7 @@
*
* @ingroup arm
*
* @brief ARM cache defines and implementation.
* @brief ARM cache dummy include for chips without cache
*/
/*
@@ -23,110 +23,36 @@
#ifndef LIBCPU_ARM_CACHE__H
#define LIBCPU_ARM_CACHE__H
#ifdef __ARM_ARCH_5TEJ__
#include <libcpu/arm-cp15.h>
/*
* The ARM targets equipped by cache should include
* which kind and implementation they support.
* Next options are available
*
* c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
* basic ARM cache integrated on the CPU core directly
* which requires only CP15 oparations
*
* c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
* support for case where ARM L2C-310 cache controller
* is used. It is accessible as mmaped peripheral.
*
* c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
* Cortex-M specific cache support
*
* Cache support should be included in BSP Makefile.am
*
* Example how to include cache support
*
* # Cache
* libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
* libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
* libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
* libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
*/
#define CPU_DATA_CACHE_ALIGNMENT 32
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
{
arm_cp15_data_cache_clean_line(d_addr);
}
static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
{
arm_cp15_data_cache_invalidate_line(d_addr);
}
static inline void _CPU_cache_freeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
{
arm_cp15_instruction_cache_invalidate_line(d_addr);
}
static inline void _CPU_cache_freeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_flush_entire_data(void)
{
arm_cp15_data_cache_test_and_clean();
}
static inline void _CPU_cache_invalidate_entire_data(void)
{
arm_cp15_data_cache_invalidate();
}
static inline void _CPU_cache_enable_data(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl |= ARM_CP15_CTRL_C;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_disable_data(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
arm_cp15_data_cache_test_and_clean_and_invalidate();
ctrl = arm_cp15_get_control();
ctrl &= ~ARM_CP15_CTRL_C;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_invalidate_entire_instruction(void)
{
arm_cp15_instruction_cache_invalidate();
}
static inline void _CPU_cache_enable_instruction(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl |= ARM_CP15_CTRL_I;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_disable_instruction(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_disable(level);
ctrl = arm_cp15_get_control();
ctrl &= ~ARM_CP15_CTRL_I;
arm_cp15_set_control(ctrl);
rtems_interrupt_enable(level);
}
#if defined(__ARM_ARCH_5TEJ__) || defined(__ARM_ARCH_7A__)
#warning ARM 5TEJ and ARMv7/Cortex-A cores include usually cache
#warning change BSP to include appropriate cache implementation
#endif
#endif /* LIBCPU_ARM_CACHE__H */