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2001-01-03 Joel Sherrill <joel@OARcorp.com>

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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
	* cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
This commit is contained in:
Joel Sherrill
2001-01-03 16:35:08 +00:00
parent ac0043451d
commit 9fd4f5c5c2
6 changed files with 40 additions and 14 deletions
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5
c/src/exec/score/cpu/mips/ChangeLog
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@@ -1,3 +1,8 @@
2001-01-03 Joel Sherrill <joel@OARcorp.com>
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
2000-12-19 Joel Sherrill <joel@OARcorp.com> 2000-12-19 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S (_ISR_Handler): Return to the address in the EPC register. * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.

12
c/src/exec/score/cpu/mips/cpu_asm.S
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@@ -57,9 +57,9 @@
#endif #endif
#ifdef __GNUC__ #ifdef __GNUC__
#define EXTERN(x,size) .extern x,size #define ASM_EXTERN(x,size) .extern x,size
#else #else
#define EXTERN(x,size) #define ASM_EXTERN(x,size)
#endif #endif
/* NOTE: these constants must match the Context_Control structure in cpu.h */ /* NOTE: these constants must match the Context_Control structure in cpu.h */
@@ -456,10 +456,10 @@ ENDFRAME(_CPU_Context_restore)
#endif #endif
EXTERN(_ISR_Nest_level, SZ_INT) ASM_EXTERN(_ISR_Nest_level, SZ_INT)
EXTERN(_Thread_Dispatch_disable_level,SZ_INT) ASM_EXTERN(_Thread_Dispatch_disable_level,SZ_INT)
EXTERN(_Context_Switch_necessary,SZ_INT) ASM_EXTERN(_Context_Switch_necessary,SZ_INT)
EXTERN(_ISR_Signals_to_thread_executing,SZ_INT) ASM_EXTERN(_ISR_Signals_to_thread_executing,SZ_INT)
.extern _Thread_Dispatch .extern _Thread_Dispatch
.extern _ISR_Vector_table .extern _ISR_Vector_table

10
c/src/exec/score/cpu/mips/rtems/score/cpu.h
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@@ -582,7 +582,15 @@ extern unsigned int mips_interrupt_number_of_vectors;
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
/* ISR handler macros */ /*
* ISR handler macros
*/
/*
* Support routine to initialize the RTEMS vector table after it is allocated.
*/
#define _CPU_Initialize_vectors()
/* /*
* Disable all interrupts for an RTEMS critical section. The previous * Disable all interrupts for an RTEMS critical section. The previous

5
cpukit/score/cpu/mips/ChangeLog
View File

@@ -1,3 +1,8 @@
2001-01-03 Joel Sherrill <joel@OARcorp.com>
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
2000-12-19 Joel Sherrill <joel@OARcorp.com> 2000-12-19 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S (_ISR_Handler): Return to the address in the EPC register. * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.

12
cpukit/score/cpu/mips/cpu_asm.S
View File

@@ -57,9 +57,9 @@
#endif #endif
#ifdef __GNUC__ #ifdef __GNUC__
#define EXTERN(x,size) .extern x,size #define ASM_EXTERN(x,size) .extern x,size
#else #else
#define EXTERN(x,size) #define ASM_EXTERN(x,size)
#endif #endif
/* NOTE: these constants must match the Context_Control structure in cpu.h */ /* NOTE: these constants must match the Context_Control structure in cpu.h */
@@ -456,10 +456,10 @@ ENDFRAME(_CPU_Context_restore)
#endif #endif
EXTERN(_ISR_Nest_level, SZ_INT) ASM_EXTERN(_ISR_Nest_level, SZ_INT)
EXTERN(_Thread_Dispatch_disable_level,SZ_INT) ASM_EXTERN(_Thread_Dispatch_disable_level,SZ_INT)
EXTERN(_Context_Switch_necessary,SZ_INT) ASM_EXTERN(_Context_Switch_necessary,SZ_INT)
EXTERN(_ISR_Signals_to_thread_executing,SZ_INT) ASM_EXTERN(_ISR_Signals_to_thread_executing,SZ_INT)
.extern _Thread_Dispatch .extern _Thread_Dispatch
.extern _ISR_Vector_table .extern _ISR_Vector_table

10
cpukit/score/cpu/mips/rtems/score/cpu.h
View File

@@ -582,7 +582,15 @@ extern unsigned int mips_interrupt_number_of_vectors;
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
/* ISR handler macros */ /*
* ISR handler macros
*/
/*
* Support routine to initialize the RTEMS vector table after it is allocated.
*/
#define _CPU_Initialize_vectors()
/* /*
* Disable all interrupts for an RTEMS critical section. The previous * Disable all interrupts for an RTEMS critical section. The previous