forked from Imagelibrary/rtems
bsp/arm: Add handling for level 2 L2C-310 cache controller
arm-l2c-310/cache_.h contains the handling for the L2C-310 level 2 cache controller from arm. It references the arm level 1 cache handling in the new file arm-cache-l1.h.
This commit is contained in:
Ralf Kirchner
committed by
Sebastian Huber
Sebastian Huber
parent
0b74e10fff
commit
9fcd1b3556
483
c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
Normal file
483
c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
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@@ -0,0 +1,483 @@
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/**
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* @file arm-cache-l1.h
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*
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* @ingroup arm_shared
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*
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* @brief Level 1 Cache definitions and functions.
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*
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* This file implements handling for the ARM Level 1 cache controller
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*/
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/*
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* Copyright (c) 2014 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef LIBBSP_ARM_SHARED_CACHE_L1_H
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#define LIBBSP_ARM_SHARED_CACHE_L1_H
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#include <assert.h>
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#include <bsp.h>
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#include <libcpu/arm-cp15.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* These two defines also ensure that the rtems_cache_* functions have bodies */
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#define ARM_CACHE_L1_CPU_DATA_ALIGNMENT 32
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#define ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT 32
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#define ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
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#define ARM_CACHE_L1_CSS_ID_DATA 0
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#define ARM_CACHE_L1_CSS_ID_INSTRUCTION 1
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#define ARM_CACHE_L1_DATA_LINE_MASK ( ARM_CACHE_L1_CPU_DATA_ALIGNMENT - 1 )
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#define ARM_CACHE_L1_INSTRUCTION_LINE_MASK \
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( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT \
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- 1 )
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/* Errata Handlers */
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#if ( defined( RTEMS_SMP ) )
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#define ARM_CACHE_L1_ERRATA_764369_HANDLER() \
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if( arm_errata_is_applicable_processor_errata_764369() ) { \
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_ARM_Data_synchronization_barrier(); \
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}
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#else /* #if ( defined( RTEMS_SMP ) ) */
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#define ARM_CACHE_L1_ERRATA_764369_HANDLER()
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#endif /* #if ( defined( RTEMS_SMP ) ) */
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static void arm_cache_l1_select( const uint32_t selection )
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{
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/* select current cache level in cssr */
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arm_cp15_set_cache_size_selection( selection );
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/* isb to sych the new cssr&csidr */
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_ARM_Instruction_synchronization_barrier();
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}
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/*
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* @param l1LineSize Number of bytes in cache line expressed as power of
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* 2 value
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* @param l1Associativity Associativity of cache. The associativity does not
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* have to be a power of 2.
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* qparam liNumSets Number of sets in cache
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* */
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static inline void arm_cache_l1_properties(
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uint32_t *l1LineSize,
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uint32_t *l1Associativity,
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uint32_t *l1NumSets )
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{
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uint32_t id;
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_ARM_Instruction_synchronization_barrier();
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id = arm_cp15_get_cache_size_id();
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/* Cache line size in words + 2 -> bytes) */
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*l1LineSize = ( id & 0x0007U ) + 2 + 2;
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/* Number of Ways */
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*l1Associativity = ( ( id >> 3 ) & 0x03ffU ) + 1;
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/* Number of Sets */
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*l1NumSets = ( ( id >> 13 ) & 0x7fffU ) + 1;
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}
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/*
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* @param log_2_line_bytes The number of bytes per cache line expressed in log2
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* @param associativity The associativity of the cache beeing operated
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* @param cache_level_idx The level of the cache beeing operated minus 1 e.g 0
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* for cache level 1
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* @param set Number of the set to operate on
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* @param way Number of the way to operate on
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* */
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static inline uint32_t arm_cache_l1_get_set_way_param(
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const uint32_t log_2_line_bytes,
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const uint32_t associativity,
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const uint32_t cache_level_idx,
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const uint32_t set,
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const uint32_t way )
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{
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uint32_t way_shift = __builtin_clz( associativity - 1 );
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return ( 0
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| ( way
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<< way_shift ) | ( set << log_2_line_bytes ) | ( cache_level_idx << 1 ) );
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}
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static inline void arm_cache_l1_flush_1_data_line( const void *d_addr )
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{
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/* Flush the Data cache */
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arm_cp15_data_cache_clean_and_invalidate_line( d_addr );
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/* Wait for L1 flush to complete */
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_ARM_Data_synchronization_barrier();
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}
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static inline void arm_cache_l1_flush_entire_data( void )
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{
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uint32_t l1LineSize, l1Associativity, l1NumSets;
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uint32_t s, w;
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uint32_t set_way_param;
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rtems_interrupt_level level;
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/* ensure ordering with previous memory accesses */
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_ARM_Data_memory_barrier();
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/* make cssr&csidr read atomic */
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rtems_interrupt_disable( level );
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/* Get the L1 cache properties */
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arm_cache_l1_properties( &l1LineSize, &l1Associativity,
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&l1NumSets );
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rtems_interrupt_enable( level );
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for ( w = 0; w < l1Associativity; ++w ) {
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for ( s = 0; s < l1NumSets; ++s ) {
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set_way_param = arm_cache_l1_get_set_way_param(
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l1LineSize,
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l1Associativity,
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0,
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s,
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w
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);
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arm_cp15_data_cache_clean_line_by_set_and_way( set_way_param );
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}
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}
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/* Wait for L1 flush to complete */
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_ARM_Data_synchronization_barrier();
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}
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static inline void arm_cache_l1_invalidate_entire_data( void )
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{
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uint32_t l1LineSize, l1Associativity, l1NumSets;
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uint32_t s, w;
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uint32_t set_way_param;
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rtems_interrupt_level level;
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/* ensure ordering with previous memory accesses */
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_ARM_Data_memory_barrier();
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/* make cssr&csidr read atomic */
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rtems_interrupt_disable( level );
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/* Get the L1 cache properties */
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arm_cache_l1_properties( &l1LineSize, &l1Associativity,
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&l1NumSets );
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rtems_interrupt_enable( level );
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for ( w = 0; w < l1Associativity; ++w ) {
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for ( s = 0; s < l1NumSets; ++s ) {
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set_way_param = arm_cache_l1_get_set_way_param(
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l1LineSize,
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l1Associativity,
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0,
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s,
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w
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);
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arm_cp15_data_cache_invalidate_line_by_set_and_way( set_way_param );
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}
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}
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/* Wait for L1 invalidate to complete */
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_ARM_Data_synchronization_barrier();
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}
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static inline void arm_cache_l1_clean_and_invalidate_entire_data( void )
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{
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uint32_t l1LineSize, l1Associativity, l1NumSets;
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uint32_t s, w;
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uint32_t set_way_param;
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rtems_interrupt_level level;
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/* ensure ordering with previous memory accesses */
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_ARM_Data_memory_barrier();
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/* make cssr&csidr read atomic */
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rtems_interrupt_disable( level );
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/* Get the L1 cache properties */
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arm_cache_l1_properties( &l1LineSize, &l1Associativity,
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&l1NumSets );
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rtems_interrupt_enable( level );
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for ( w = 0; w < l1Associativity; ++w ) {
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for ( s = 0; s < l1NumSets; ++s ) {
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set_way_param = arm_cache_l1_get_set_way_param(
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l1LineSize,
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l1Associativity,
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0,
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s,
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w
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);
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arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(
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set_way_param );
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}
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}
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/* Wait for L1 invalidate to complete */
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_ARM_Data_synchronization_barrier();
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}
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static inline void arm_cache_l1_store_data( const void *d_addr )
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{
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/* Store the Data cache line */
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arm_cp15_data_cache_clean_line( d_addr );
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/* Wait for L1 store to complete */
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_ARM_Data_synchronization_barrier();
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}
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static inline void arm_cache_l1_flush_data_range(
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const void *d_addr,
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size_t n_bytes
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)
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{
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if ( n_bytes != 0 ) {
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uint32_t adx = (uint32_t) d_addr
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& ~ARM_CACHE_L1_DATA_LINE_MASK;
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const uint32_t ADDR_LAST =
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( (uint32_t) d_addr + n_bytes - 1 ) & ~ARM_CACHE_L1_DATA_LINE_MASK;
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ARM_CACHE_L1_ERRATA_764369_HANDLER();
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for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
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/* Store the Data cache line */
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arm_cp15_data_cache_clean_line( (void*)adx );
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}
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/* Wait for L1 store to complete */
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_ARM_Data_synchronization_barrier();
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}
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}
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static inline void arm_cache_l1_invalidate_1_data_line(
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const void *d_addr )
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{
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/* Invalidate the data cache line */
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arm_cp15_data_cache_invalidate_line( d_addr );
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/* Wait for L1 invalidate to complete */
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_ARM_Data_synchronization_barrier();
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}
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static inline void arm_cache_l1_freeze_data( void )
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{
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/* To be implemented as needed, if supported by hardware at all */
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}
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static inline void arm_cache_l1_unfreeze_data( void )
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{
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/* To be implemented as needed, if supported by hardware at all */
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}
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static inline void arm_cache_l1_invalidate_1_instruction_line(
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const void *i_addr )
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{
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/* Invalidate the Instruction cache line */
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arm_cp15_instruction_cache_invalidate_line( i_addr );
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/* Wait for L1 invalidate to complete */
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_ARM_Data_synchronization_barrier();
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}
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static inline void arm_cache_l1_invalidate_data_range(
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const void *d_addr,
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size_t n_bytes
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)
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{
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if ( n_bytes != 0 ) {
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uint32_t adx = (uint32_t) d_addr
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& ~ARM_CACHE_L1_DATA_LINE_MASK;
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const uint32_t end =
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( adx + n_bytes ) & ~ARM_CACHE_L1_DATA_LINE_MASK;
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ARM_CACHE_L1_ERRATA_764369_HANDLER();
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/* Back starting address up to start of a line and invalidate until end */
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for (;
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adx < end;
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adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
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/* Invalidate the Instruction cache line */
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arm_cp15_data_cache_invalidate_line( (void*)adx );
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}
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/* Wait for L1 invalidate to complete */
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_ARM_Data_synchronization_barrier();
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}
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}
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static inline void arm_cache_l1_invalidate_instruction_range(
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const void *i_addr,
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size_t n_bytes
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)
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{
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if ( n_bytes != 0 ) {
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uint32_t adx = (uint32_t) i_addr
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& ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK;
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const uint32_t end =
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( adx + n_bytes ) & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK;
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arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
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ARM_CACHE_L1_ERRATA_764369_HANDLER();
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/* Back starting address up to start of a line and invalidate until end */
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for (;
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adx < end;
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adx += ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT ) {
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/* Invalidate the Instruction cache line */
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arm_cp15_instruction_cache_invalidate_line( (void*)adx );
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}
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/* Wait for L1 invalidate to complete */
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_ARM_Data_synchronization_barrier();
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arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
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}
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}
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static inline void arm_cache_l1_invalidate_entire_instruction( void )
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{
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uint32_t ctrl = arm_cp15_get_control();
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#ifdef RTEMS_SMP
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/* invalidate I-cache inner shareable */
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arm_cp15_instruction_cache_inner_shareable_invalidate_all();
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/* I+BTB cache invalidate */
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arm_cp15_instruction_cache_invalidate();
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#else /* RTEMS_SMP */
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/* I+BTB cache invalidate */
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arm_cp15_instruction_cache_invalidate();
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#endif /* RTEMS_SMP */
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if ( ( ctrl & ARM_CP15_CTRL_Z ) == 0 ) {
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arm_cp15_branch_predictor_inner_shareable_invalidate_all();
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arm_cp15_branch_predictor_invalidate_all();
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}
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}
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static inline void arm_cache_l1_freeze_instruction( void )
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{
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/* To be implemented as needed, if supported by hardware at all */
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}
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static inline void arm_cache_l1_unfreeze_instruction( void )
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{
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/* To be implemented as needed, if supported by hardware at all */
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}
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static inline void arm_cache_l1_enable_data( void )
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{
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rtems_interrupt_level level;
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uint32_t ctrl;
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arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
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assert( ARM_CACHE_L1_CPU_DATA_ALIGNMENT == arm_cp15_get_data_cache_line_size() );
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rtems_interrupt_disable( level );
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ctrl = arm_cp15_get_control();
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rtems_interrupt_enable( level );
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/* Only enable the cache if it is disabled */
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if ( !( ctrl & ARM_CP15_CTRL_C ) ) {
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/* Clean and invalidate the Data cache */
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arm_cache_l1_invalidate_entire_data();
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/* Enable the Data cache */
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ctrl |= ARM_CP15_CTRL_C;
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rtems_interrupt_disable( level );
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arm_cp15_set_control( ctrl );
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rtems_interrupt_enable( level );
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}
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}
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static inline void arm_cache_l1_disable_data( void )
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{
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rtems_interrupt_level level;
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/* Clean and invalidate the Data cache */
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arm_cache_l1_flush_entire_data();
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rtems_interrupt_disable( level );
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/* Disable the Data cache */
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arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_C );
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rtems_interrupt_enable( level );
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}
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static inline void arm_cache_l1_disable_instruction( void )
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable( level );
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/* Synchronize the processor */
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_ARM_Data_synchronization_barrier();
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/* Invalidate the Instruction cache */
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arm_cache_l1_invalidate_entire_instruction();
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/* Disable the Instruction cache */
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arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_I );
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rtems_interrupt_enable( level );
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}
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static inline void arm_cache_l1_enable_instruction( void )
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{
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rtems_interrupt_level level;
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uint32_t ctrl;
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arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
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assert( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
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== arm_cp15_get_data_cache_line_size() );
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rtems_interrupt_disable( level );
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/* Enable Instruction cache only if it is disabled */
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ctrl = arm_cp15_get_control();
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if ( !( ctrl & ARM_CP15_CTRL_I ) ) {
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/* Invalidate the Instruction cache */
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arm_cache_l1_invalidate_entire_instruction();
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/* Enable the Instruction cache */
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ctrl |= ARM_CP15_CTRL_I;
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arm_cp15_set_control( ctrl );
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}
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rtems_interrupt_enable( level );
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arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
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}
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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||||
|
||||
#endif /* LIBBSP_ARM_SHARED_CACHE_L1_H */
|
||||
Reference in New Issue
Block a user