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libcpu/sh/sh7750/clock/ckinit.c: Fix warnings

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This commit is contained in:
Joel Sherrill
2014-10-12 15:37:34 -05:00
parent 4172cf1b2b
commit 9fab016dac
1 changed files with 127 additions and 163 deletions
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290
c/src/lib/libcpu/sh/sh7750/clock/ckinit.c
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@@ -1,6 +1,8 @@
/* /*
* This file contains the generic RTEMS clock driver the Hitachi SH 7750 * This file contains the generic RTEMS clock driver the Hitachi SH 7750
* */
/*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru> * Author: Victor V. Vengerov <vvv@oktet.ru>
* *
@@ -16,7 +18,7 @@
#include <stdlib.h> #include <stdlib.h>
#include <rtems/libio.h> #include <rtems/clockdrv.h>
#include <rtems/score/sh_io.h> #include <rtems/score/sh_io.h>
#include <rtems/score/sh.h> #include <rtems/score/sh.h>
#include <rtems/score/ispsh7750.h> #include <rtems/score/ispsh7750.h>
@@ -36,198 +38,171 @@ extern uint32_t bsp_clicks_per_second;
* The interrupt vector number associated with the clock tick device * The interrupt vector number associated with the clock tick device
* driver. * driver.
*/ */
#define CLOCK_VECTOR SH7750_EVT_TO_NUM(SH7750_EVT_TUNI0) #define CLOCK_VECTOR SH7750_EVT_TO_NUM(SH7750_EVT_TUNI0)
/* /*
* Clock_driver_ticks is a monotonically increasing counter of the * Clock_driver_ticks is a monotonically increasing counter of the
* number of clock ticks since the driver was initialized. * number of clock ticks since the driver was initialized.
*/ */
volatile uint32_t Clock_driver_ticks; volatile uint32_t Clock_driver_ticks;
static void Clock_exit( void );
static rtems_isr Clock_isr( rtems_vector_number vector ); static rtems_isr Clock_isr( rtems_vector_number vector );
/*
* These are set by clock driver during its init
*/
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
/* /*
* The previous ISR on this clock tick interrupt vector. * The previous ISR on this clock tick interrupt vector.
*/ */
rtems_isr_entry Old_ticker; rtems_isr_entry Old_ticker;
/* /*
* Isr Handler * Isr Handler
*/ */
/* Clock_isr -- /*
* Clock interrupt handling routine. * Clock_isr
* *
* PARAMETERS: * Clock interrupt handling routine.
* vector - interrupt vector number
*
* RETURNS:
* none
*/ */
rtems_isr static rtems_isr Clock_isr(rtems_vector_number vector)
Clock_isr(rtems_vector_number vector)
{ {
uint16_t tcr; uint16_t tcr;
/* reset the timer underflow flag */ /* reset the timer underflow flag */
tcr = read16(SH7750_TCR0); tcr = read16(SH7750_TCR0);
write16(tcr & ~SH7750_TCR_UNF, SH7750_TCR0); write16(tcr & ~SH7750_TCR_UNF, SH7750_TCR0);
/* Increment the clock interrupt counter */ /* Increment the clock interrupt counter */
Clock_driver_ticks++ ; Clock_driver_ticks++ ;
/* Invoke rtems clock service routine */ /* Invoke rtems clock service routine */
rtems_clock_tick(); rtems_clock_tick();
} }
/* Install_clock -- /*
* Install a clock tick handler and reprograms the chip. This * Install_clock
* is used to initially establish the clock tick.
* *
* PARAMETERS: * Install a clock tick handler and reprograms the chip. This
* clock_isr - Clock interrupt stay routine * is used to initially establish the clock tick.
*
* RETURNS:
* none
* *
* SIDE EFFECTS: * SIDE EFFECTS:
* Establish clock interrupt handler, configure Timer 0 hardware * Establish clock interrupt handler, configure Timer 0 hardware
*/ */
void static void Install_clock(rtems_isr_entry clock_isr)
Install_clock(rtems_isr_entry clock_isr)
{ {
int cpudiv = 1; /* CPU frequency divider */ int cpudiv = 1; /* CPU frequency divider */
int tidiv = 1; /* Timer input frequency divider */ int tidiv = 1; /* Timer input frequency divider */
uint32_t timer_divider; /* Calculated Timer Divider value */ uint32_t timer_divider; /* Calculated Timer Divider value */
uint8_t temp8; uint8_t temp8;
uint16_t temp16; uint16_t temp16;
/* /*
* Initialize the clock tick device driver variables * Initialize the clock tick device driver variables
*/ */
Clock_driver_ticks = 0; Clock_driver_ticks = 0;
/* Get CPU frequency divider from clock unit */ /* Get CPU frequency divider from clock unit */
switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC) switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC) {
{ case SH7750_FRQCR_IFCDIV1:
case SH7750_FRQCR_IFCDIV1: cpudiv = 1;
cpudiv = 1; break;
break;
case SH7750_FRQCR_IFCDIV2: case SH7750_FRQCR_IFCDIV2:
cpudiv = 2; cpudiv = 2;
break; break;
case SH7750_FRQCR_IFCDIV3: case SH7750_FRQCR_IFCDIV3:
cpudiv = 3; cpudiv = 3;
break; break;
case SH7750_FRQCR_IFCDIV4: case SH7750_FRQCR_IFCDIV4:
cpudiv = 4; cpudiv = 4;
break; break;
case SH7750_FRQCR_IFCDIV6: case SH7750_FRQCR_IFCDIV6:
cpudiv = 6; cpudiv = 6;
break; break;
case SH7750_FRQCR_IFCDIV8: case SH7750_FRQCR_IFCDIV8:
cpudiv = 8; cpudiv = 8;
break; break;
default: default:
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
} }
/* Get peripheral module frequency divider from clock unit */ /* Get peripheral module frequency divider from clock unit */
switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC) switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC) {
{ case SH7750_FRQCR_PFCDIV2:
case SH7750_FRQCR_PFCDIV2: tidiv = 2 * CLOCK_PRESCALER;
tidiv = 2 * CLOCK_PRESCALER; break;
break;
case SH7750_FRQCR_PFCDIV3: case SH7750_FRQCR_PFCDIV3:
tidiv = 3 * CLOCK_PRESCALER; tidiv = 3 * CLOCK_PRESCALER;
break; break;
case SH7750_FRQCR_PFCDIV4: case SH7750_FRQCR_PFCDIV4:
tidiv = 4 * CLOCK_PRESCALER; tidiv = 4 * CLOCK_PRESCALER;
break; break;
case SH7750_FRQCR_PFCDIV6: case SH7750_FRQCR_PFCDIV6:
tidiv = 6 * CLOCK_PRESCALER; tidiv = 6 * CLOCK_PRESCALER;
break; break;
case SH7750_FRQCR_PFCDIV8: case SH7750_FRQCR_PFCDIV8:
tidiv = 8 * CLOCK_PRESCALER; tidiv = 8 * CLOCK_PRESCALER;
break; break;
default: default:
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
} }
timer_divider = timer_divider =
(bsp_clicks_per_second * cpudiv / (tidiv*1000000)) * (bsp_clicks_per_second * cpudiv / (tidiv*1000000)) *
rtems_configuration_get_microseconds_per_tick(); rtems_configuration_get_microseconds_per_tick();
/* /*
* Hardware specific initialization * Hardware specific initialization
*/ */
/* Stop the Timer 0 */ /* Stop the Timer 0 */
temp8 = read8(SH7750_TSTR); temp8 = read8(SH7750_TSTR);
temp8 &= ~SH7750_TSTR_STR0; temp8 &= ~SH7750_TSTR_STR0;
write8(temp8, SH7750_TSTR); write8(temp8, SH7750_TSTR);
/* Establish interrupt handler */ /* Establish interrupt handler */
rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker ); rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
/* Reset counter */ /* Reset counter */
write32(timer_divider, SH7750_TCNT0); write32(timer_divider, SH7750_TCNT0);
/* Load divider */ /* Load divider */
write32(timer_divider, SH7750_TCOR0); write32(timer_divider, SH7750_TCOR0);
write16( write16(
SH7750_TCR_UNIE | /* Enable Underflow Interrupt */ SH7750_TCR_UNIE | /* Enable Underflow Interrupt */
SH7750_TCR_CKEG_RAISE | /* Count on rising edge */ SH7750_TCR_CKEG_RAISE | /* Count on rising edge */
TCR0_TPSC, /* Timer prescaler ratio */ TCR0_TPSC, /* Timer prescaler ratio */
SH7750_TCR0); SH7750_TCR0);
/* Set clock interrupt priority */ /* Set clock interrupt priority */
temp16 = read16(SH7750_IPRA); temp16 = read16(SH7750_IPRA);
temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (CLOCKPRIO << SH7750_IPRA_TMU0_S); temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (CLOCKPRIO << SH7750_IPRA_TMU0_S);
write16(temp16, SH7750_IPRA); write16(temp16, SH7750_IPRA);
/* Start the Timer 0 */ /* Start the Timer 0 */
temp8 = read8(SH7750_TSTR); temp8 = read8(SH7750_TSTR);
temp8 |= SH7750_TSTR_STR0; temp8 |= SH7750_TSTR_STR0;
write8(temp8, SH7750_TSTR); write8(temp8, SH7750_TSTR);
/* /*
* Schedule the clock cleanup routine to execute if the application exits. * Schedule the clock cleanup routine to execute if the application exits.
*/ */
atexit( Clock_exit );
atexit( Clock_exit );
} }
/* Clock_exit -- /*
* Clean up before the application exits * Clock_exit
* *
* PARAMETERS: * Clean up before the application exits
* none
*
* RETURNS:
* none
* *
* SIDE EFFECTS: * SIDE EFFECTS:
* Stop Timer 0 counting, set timer 0 interrupt priority level to 0. * Stop Timer 0 counting, set timer 0 interrupt priority level to 0.
@@ -235,46 +210,35 @@ Install_clock(rtems_isr_entry clock_isr)
void void
Clock_exit(void) Clock_exit(void)
{ {
uint8_t temp8 = 0; uint8_t temp8 = 0;
uint16_t temp16 = 0; uint16_t temp16 = 0;
/* turn off the timer interrupts */ /* turn off the timer interrupts */
/* Stop the Timer 0 */ /* Stop the Timer 0 */
temp8 = read8(SH7750_TSTR); temp8 = read8(SH7750_TSTR);
temp8 &= ~SH7750_TSTR_STR0; temp8 &= ~SH7750_TSTR_STR0;
write8(temp8, SH7750_TSTR); write8(temp8, SH7750_TSTR);
/* Lower timer interrupt priority to 0 */ /* Lower timer interrupt priority to 0 */
temp16 = read16(SH7750_IPRA); temp16 = read16(SH7750_IPRA);
temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (0 << SH7750_IPRA_TMU0_S); temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (0 << SH7750_IPRA_TMU0_S);
write16(temp16, SH7750_IPRA); write16(temp16, SH7750_IPRA);
/* old vector shall not be installed */ /* old vector shall not be installed */
} }
/* Clock_initialize -- /*
* Device driver entry point for clock tick driver initialization. * Clock_initialize
* *
* PARAMETERS: * Device driver entry point for clock tick driver initialization.
* major - clock major device number
* minor - clock minor device number
* pargp - driver initialize primitive argument, not used
*
* RETURNS:
* RTEMS_SUCCESSFUL
*/ */
rtems_device_driver rtems_device_driver Clock_initialize(
Clock_initialize(rtems_device_major_number major, rtems_device_major_number major,
rtems_device_minor_number minor, rtems_device_minor_number minor,
void *pargp) void *pargp
)
{ {
Install_clock( Clock_isr ); Install_clock( Clock_isr );
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL; return RTEMS_SUCCESSFUL;
} }