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bsp/arm: Consistenly same handling for flushing

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It is importeant to consistently apply the same handling for flushing within
level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
This commit is contained in:
Ralf Kirchner
2014-04-17 09:43:30 +02:00
committed by Sebastian Huber
parent e331e69a47
commit 9ee2ec56b5
1 changed files with 2 additions and 2 deletions
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4
c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
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@@ -252,8 +252,8 @@ static inline void arm_cache_l1_flush_data_range(
ARM_CACHE_L1_ERRATA_764369_HANDLER(); ARM_CACHE_L1_ERRATA_764369_HANDLER();
for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) { for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
/* Store the Data cache line */ /* Store and invalidate the Data cache line */
arm_cp15_data_cache_clean_line( (void*)adx ); arm_cp15_data_cache_clean_and_invalidate_line( (void*)adx );
} }
/* Wait for L1 store to complete */ /* Wait for L1 store to complete */
_ARM_Data_synchronization_barrier(); _ARM_Data_synchronization_barrier();