forked from Imagelibrary/rtems
2005-04-26 Joel Sherrill <joel@OARcorp.com>
* console/uart.h: Eliminate tabs.
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,7 @@
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2005-04-26 Joel Sherrill <joel@OARcorp.com>
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* console/uart.h: Eliminate tabs.
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2005-04-15 Jennifer Averett <jennifer.averett@oarcorp.com>
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PR 779/bsp
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@@ -45,18 +45,20 @@ extern int BSPBaseBaud;
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/* pass a BSP_UartBreakCb pointer to ioctl when retrieving
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* or installing break callback
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*/
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typedef void (*BSP_UartBreakCbProc)(int uartMinor,
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unsigned uartRBRLSRStatus,
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void *termiosPrivatePtr,
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void *private);
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typedef void (*BSP_UartBreakCbProc)(
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int uartMinor,
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unsigned uartRBRLSRStatus,
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void *termiosPrivatePtr,
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void *private
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);
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typedef struct BSP_UartBreakCbRec_ {
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BSP_UartBreakCbProc handler; /* NOTE NOTE this handler runs in INTERRUPT CONTEXT */
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void *private; /* closure pointer which is passed to the callback */
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BSP_UartBreakCbProc handler; /* NOTE: handler runs in INTERRUPT CONTEXT */
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void *private; /* closure pointer which is passed to the callback */
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} BSP_UartBreakCbRec, *BSP_UartBreakCb;
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#define BIOCGETBREAKCB _IOR('b',1,sizeof(BSP_UartBreakCbRec))
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#define BIOCSETBREAKCB _IOW('b',2,sizeof(BSP_UartBreakCbRec))
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#define BIOCGETBREAKCB _IOR('b',1,sizeof(BSP_UartBreakCbRec))
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#define BIOCSETBREAKCB _IOW('b',2,sizeof(BSP_UartBreakCbRec))
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/*
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* Command values for BSP_uart_intr_ctrl(),
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@@ -104,42 +106,42 @@ typedef struct BSP_UartBreakCbRec_ {
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/*
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* Interrupt source definition via IIR
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*/
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#define MODEM_STATUS 0
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#define NO_MORE_INTR 1
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#define TRANSMITTER_HODING_REGISTER_EMPTY 2
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#define RECEIVER_DATA_AVAIL 4
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#define RECEIVER_ERROR 6
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#define CHARACTER_TIMEOUT_INDICATION 12
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#define MODEM_STATUS 0
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#define NO_MORE_INTR 1
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#define TRANSMITTER_HODING_REGISTER_EMPTY 2
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#define RECEIVER_DATA_AVAIL 4
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#define RECEIVER_ERROR 6
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#define CHARACTER_TIMEOUT_INDICATION 12
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/*
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* Bits definition of IER
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*/
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#define RECEIVE_ENABLE 0x1
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#define TRANSMIT_ENABLE 0x2
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#define RECEIVER_LINE_ST_ENABLE 0x4
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#define MODEM_ENABLE 0x8
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#define INTERRUPT_DISABLE 0x0
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#define RECEIVE_ENABLE 0x1
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#define TRANSMIT_ENABLE 0x2
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#define RECEIVER_LINE_ST_ENABLE 0x4
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#define MODEM_ENABLE 0x8
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#define INTERRUPT_DISABLE 0x0
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/*
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* Bits definition of the Line Status Register (LSR)
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*/
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#define DR 0x01 /* Data Ready */
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#define OE 0x02 /* Overrun Error */
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#define PE 0x04 /* Parity Error */
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#define FE 0x08 /* Framing Error */
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#define BI 0x10 /* Break Interrupt */
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#define THRE 0x20 /* Transmitter Holding Register Empty */
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#define TEMT 0x40 /* Transmitter Empty */
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#define ERFIFO 0x80 /* Error receive Fifo */
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#define DR 0x01 /* Data Ready */
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#define OE 0x02 /* Overrun Error */
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#define PE 0x04 /* Parity Error */
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#define FE 0x08 /* Framing Error */
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#define BI 0x10 /* Break Interrupt */
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#define THRE 0x20 /* Transmitter Holding Register Empty */
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#define TEMT 0x40 /* Transmitter Empty */
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#define ERFIFO 0x80 /* Error receive Fifo */
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/*
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* Bits definition of the MODEM Control Register (MCR)
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*/
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#define DTR 0x01 /* Data Terminal Ready */
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#define RTS 0x02 /* Request To Send */
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#define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */
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#define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */
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#define LB 0x10 /* Enable Internal Loop Back */
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#define DTR 0x01 /* Data Terminal Ready */
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#define RTS 0x02 /* Request To Send */
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#define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */
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#define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */
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#define LB 0x10 /* Enable Internal Loop Back */
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/*
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* Bits definition of the Line Control Register (LCR)
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@@ -149,40 +151,40 @@ typedef struct BSP_UartBreakCbRec_ {
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#define CHR_7_BITS 2
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#define CHR_8_BITS 3
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#define WL 0x03 /* Word length mask */
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#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */
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#define PEN 0x08 /* Parity Enabled */
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#define EPS 0x10 /* Even Parity Select, otherwise Odd */
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#define SP 0x20 /* Stick Parity */
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#define BCB 0x40 /* Break Control Bit */
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#define DLAB 0x80 /* Enable Divisor Latch Access */
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#define WL 0x03 /* Word length mask */
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#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */
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#define PEN 0x08 /* Parity Enabled */
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#define EPS 0x10 /* Even Parity Select, otherwise Odd */
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#define SP 0x20 /* Stick Parity */
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#define BCB 0x40 /* Break Control Bit */
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#define DLAB 0x80 /* Enable Divisor Latch Access */
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/*
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* Bits definition of the MODEM Status Register (MSR)
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*/
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#define DCTS 0x01 /* Delta Clear To Send */
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#define DDSR 0x02 /* Delta Data Set Ready */
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#define TERI 0x04 /* Trailing Edge Ring Indicator */
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#define DDCD 0x08 /* Delta Carrier Detect Indicator */
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#define CTS 0x10 /* Clear To Send (when loop back is active) */
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#define DSR 0x20 /* Data Set Ready (when loop back is active) */
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#define RI 0x40 /* Ring Indicator (when loop back is active) */
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#define DCD 0x80 /* Data Carrier Detect (when loop back is active) */
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#define DCTS 0x01 /* Delta Clear To Send */
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#define DDSR 0x02 /* Delta Data Set Ready */
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#define TERI 0x04 /* Trailing Edge Ring Indicator */
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#define DDCD 0x08 /* Delta Carrier Detect Indicator */
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#define CTS 0x10 /* Clear To Send (when loop back is active) */
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#define DSR 0x20 /* Data Set Ready (when loop back is active) */
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#define RI 0x40 /* Ring Indicator (when loop back is active) */
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#define DCD 0x80 /* Data Carrier Detect (when loop back is active) */
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/*
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* Bits definition of the FIFO Control Register : WD16C552 or NS16550
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*/
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#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */
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#define FIFO_EN 0x01 /* Enable the FIFO */
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#define XMIT_RESET 0x02 /* Transmit FIFO Reset */
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#define RCV_RESET 0x04 /* Receive FIFO Reset */
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#define FCR3 0x08 /* do not understand manual! */
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#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */
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#define FIFO_EN 0x01 /* Enable the FIFO */
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#define XMIT_RESET 0x02 /* Transmit FIFO Reset */
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#define RCV_RESET 0x04 /* Receive FIFO Reset */
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#define FCR3 0x08 /* do not understand manual! */
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#define RECEIVE_FIFO_TRIGGER1 0x0 /* trigger recieve interrupt after 1 byte */
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#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger recieve interrupt after 4 byte */
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#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger recieve interrupt after 8 byte */
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#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger recieve interrupt after 12 byte */
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#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */
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#define RECEIVE_FIFO_TRIGGER1 0x00 /* trigger RX interrupt after 1 byte */
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#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger RX interrupt after 4 bytes */
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#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger RX interrupt after 8 bytes */
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#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger RX interrupt after 12 bytes */
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#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */
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#endif /* _BSPUART_H */
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