forked from Imagelibrary/rtems
Renamed
This commit is contained in:
Joel Sherrill
@@ -1,142 +0,0 @@
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@c
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@c Timing information for PSIM
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@c
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@c COPYRIGHT (c) 1988-1998.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@include ../../common/timemac.texi
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@tex
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\global\advance \smallskipamount by -4pt
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@end tex
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@ifinfo
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@node RTEMS_BSP Timing Data, RTEMS_BSP Timing Data Introduction, Timing Specification Terminology, Top
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@end ifinfo
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@chapter RTEMS_BSP Timing Data
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@ifinfo
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@menu
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* RTEMS_BSP Timing Data Introduction::
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* RTEMS_BSP Timing Data Hardware Platform::
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* RTEMS_BSP Timing Data Interrupt Latency::
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* RTEMS_BSP Timing Data Context Switch::
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* RTEMS_BSP Timing Data Directive Times::
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* RTEMS_BSP Timing Data Task Manager::
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* RTEMS_BSP Timing Data Interrupt Manager::
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* RTEMS_BSP Timing Data Clock Manager::
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* RTEMS_BSP Timing Data Timer Manager::
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* RTEMS_BSP Timing Data Semaphore Manager::
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* RTEMS_BSP Timing Data Message Manager::
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* RTEMS_BSP Timing Data Event Manager::
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* RTEMS_BSP Timing Data Signal Manager::
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* RTEMS_BSP Timing Data Partition Manager::
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* RTEMS_BSP Timing Data Region Manager::
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* RTEMS_BSP Timing Data Dual-Ported Memory Manager::
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* RTEMS_BSP Timing Data I/O Manager::
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* RTEMS_BSP Timing Data Rate Monotonic Manager::
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@end menu
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@end ifinfo
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@ifinfo
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@node RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data, RTEMS_BSP Timing Data
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@end ifinfo
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@section Introduction
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The timing data for RTEMS on the RTEMS_BSP target
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is provided along with the target
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dependent aspects concerning the gathering of the timing data.
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The hardware platform used to gather the times is described to
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give the reader a better understanding of each directive time
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provided. Also, provided is a description of the interrupt
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latency and the context switch times as they pertain to the
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PowerPC version of RTEMS.
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@ifinfo
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@node RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data
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@end ifinfo
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@section Hardware Platform
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All times reported in this chapter were measured using the PowerPC
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Instruction Simulator (PSIM). PSIM simulates a variety of PowerPC
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6xx models with the PPC603e being used as the basis for the measurements
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reported in this chapter.
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The PowerPC decrementer register was was used to gather
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all timing information. In real hardware implementations
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of the PowerPC architecture, this register would typically
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count something like CPU cycles or be a function of the clock
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speed. However, with PSIM each count of the decrementer register
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represents an instruction. Thus all measurements in this
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chapter are reported as the actual number of instructions
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executed. All sources of hardware interrupts were disabled,
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although traps were enabled and the interrupt level of the
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PowerPC allows all interrupts.
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@ifinfo
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@node RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data
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@end ifinfo
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@section Interrupt Latency
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The maximum period with traps disabled or the
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processor interrupt level set to it's highest value inside RTEMS
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is less than RTEMS_MAXIMUM_DISABLE_PERIOD
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microseconds including the instructions which
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disable and re-enable interrupts. The time required for the
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PowerPC to vector an interrupt and for the RTEMS entry overhead
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before invoking the user's trap handler are a total of
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RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
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microseconds. These combine to yield a worst case interrupt
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latency of less than RTEMS_MAXIMUM_DISABLE_PERIOD +
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RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK microseconds at
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RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz.
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[NOTE: The maximum period with interrupts disabled was last
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determined for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
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The maximum period with interrupts disabled within
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RTEMS is hand-timed with some assistance from RTEMS_BSP. The maximum
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period with interrupts disabled with RTEMS occurs was not measured
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on this target.
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The interrupt vector and entry overhead time was
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generated on the RTEMS_BSP benchmark platform using the PowerPC's
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decrementer register. This register was programmed to generate
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an interrupt after one countdown.
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@ifinfo
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@node RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Directive Times, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data
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@end ifinfo
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@section Context Switch
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The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
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instructions on the RTEMS_BSP benchmark platform when no floating
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point context is saved or restored. Additional execution time
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is required when a TASK_SWITCH user extension is configured.
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The use of the TASK_SWITCH extension is application dependent.
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Thus, its execution time is not considered part of the raw
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context switch time.
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Since RTEMS was designed specifically for embedded
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missile applications which are floating point intensive, the
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executive is optimized to avoid unnecessarily saving and
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restoring the state of the numeric coprocessor. The state of
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the numeric coprocessor is only saved when an FLOATING_POINT
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task is dispatched and that task was not the last task to
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utilize the coprocessor. In a system with only one
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FLOATING_POINT task, the state of the numeric coprocessor will
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never be saved or restored. When the first FLOATING_POINT task
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is dispatched, RTEMS does not need to save the current state of
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the numeric coprocessor.
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The following table summarizes the context switch
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times for the RTEMS_BSP benchmark platform:
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@include timetbl.texi
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@tex
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\global\advance \smallskipamount by 4pt
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@end tex
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@@ -1,157 +0,0 @@
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@c
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@c Timing information for the DMV177
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@c
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@c COPYRIGHT (c) 1988-1998.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@include ../../common/timemac.texi
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@tex
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\global\advance \smallskipamount by -4pt
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@end tex
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@ifinfo
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@node RTEMS_BSP Timing Data, RTEMS_BSP Timing Data Introduction, PSIM Timing Data Rate Monotonic Manager, Top
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@end ifinfo
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@chapter RTEMS_BSP Timing Data
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@ifinfo
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@menu
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* RTEMS_BSP Timing Data Introduction::
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* RTEMS_BSP Timing Data Hardware Platform::
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* RTEMS_BSP Timing Data Interrupt Latency::
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* RTEMS_BSP Timing Data Context Switch::
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* RTEMS_BSP Timing Data Directive Times::
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* RTEMS_BSP Timing Data Task Manager::
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* RTEMS_BSP Timing Data Interrupt Manager::
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* RTEMS_BSP Timing Data Clock Manager::
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* RTEMS_BSP Timing Data Timer Manager::
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* RTEMS_BSP Timing Data Semaphore Manager::
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* RTEMS_BSP Timing Data Message Manager::
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* RTEMS_BSP Timing Data Event Manager::
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* RTEMS_BSP Timing Data Signal Manager::
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* RTEMS_BSP Timing Data Partition Manager::
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* RTEMS_BSP Timing Data Region Manager::
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* RTEMS_BSP Timing Data Dual-Ported Memory Manager::
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* RTEMS_BSP Timing Data I/O Manager::
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* RTEMS_BSP Timing Data Rate Monotonic Manager::
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@end menu
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@end ifinfo
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@ifinfo
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@node RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data, RTEMS_BSP Timing Data
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@end ifinfo
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@section Introduction
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The timing data for RTEMS on the DY-4 RTEMS_BSP board
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is provided along with the target
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dependent aspects concerning the gathering of the timing data.
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The hardware platform used to gather the times is described to
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give the reader a better understanding of each directive time
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provided. Also, provided is a description of the interrupt
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latency and the context switch times as they pertain to the
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PowerPC version of RTEMS.
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@ifinfo
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@node RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data
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@end ifinfo
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@section Hardware Platform
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All times reported in this chapter were measured using a RTEMS_BSP board.
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All data and code caching was disabled. This results in very deterministic
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times which represent the worst possible performance. Many embedded
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applications disable caching to insure that execution times are
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repeatable. Moreover, the JTAG port on certain revisions of the PowerPC
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603e does not operate properly if caching is enabled. Thus during
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development and debug, caching must be off.
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The PowerPC decrementer register was was used to gather
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all timing information. In the PowerPC architecture,
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this register typically counts
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something like CPU cycles or is a function of the clock
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speed. On the PPC603e decrements once for every four (4) bus cycles.
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On the RTEMS_BSP, the bus operates at a clock speed of
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33 Mhz. This result in a very accurate number since it is a function of the
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microprocessor itself. Thus all measurements in this
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chapter are reported as the actual number of decrementer
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clicks reported.
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To convert the numbers reported to microseconds, one should
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divide the number reported by 8.650752. This number was derived as
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shown below:
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@example
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((33 * 1048576) / 1000000) / 4 = 8.650752
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@end example
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All sources of hardware interrupts were disabled,
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although traps were enabled and the interrupt level of the
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PowerPC allows all interrupts.
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@ifinfo
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@node RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data
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@end ifinfo
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@section Interrupt Latency
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The maximum period with traps disabled or the
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processor interrupt level set to it's highest value inside RTEMS
|
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is less than RTEMS_MAXIMUM_DISABLE_PERIOD
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microseconds including the instructions which
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disable and re-enable interrupts. The time required for the
|
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PowerPC to vector an interrupt and for the RTEMS entry overhead
|
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before invoking the user's trap handler are a total of
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RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
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microseconds. These combine to yield a worst case interrupt
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latency of less than RTEMS_MAXIMUM_DISABLE_PERIOD +
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RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK microseconds at
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RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz.
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[NOTE: The maximum period with interrupts disabled was last
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determined for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
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||||
|
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The maximum period with interrupts disabled within
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RTEMS is hand-timed with some assistance from the PowerPC simulator.
|
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The maximum period with interrupts disabled with RTEMS has not
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||||
been calculated on this target.
|
||||
|
||||
The interrupt vector and entry overhead time was
|
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generated on the PSIM benchmark platform using the PowerPC's
|
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decrementer register. This register was programmed to generate
|
||||
an interrupt after one countdown.
|
||||
|
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@ifinfo
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||||
@node RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Directive Times, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data
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@end ifinfo
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@section Context Switch
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The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
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bus cycle on the RTEMS_BSP benchmark platform when no floating
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point context is saved or restored. Additional execution time
|
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is required when a TASK_SWITCH user extension is configured.
|
||||
The use of the TASK_SWITCH extension is application dependent.
|
||||
Thus, its execution time is not considered part of the raw
|
||||
context switch time.
|
||||
|
||||
Since RTEMS was designed specifically for embedded
|
||||
missile applications which are floating point intensive, the
|
||||
executive is optimized to avoid unnecessarily saving and
|
||||
restoring the state of the numeric coprocessor. The state of
|
||||
the numeric coprocessor is only saved when an FLOATING_POINT
|
||||
task is dispatched and that task was not the last task to
|
||||
utilize the coprocessor. In a system with only one
|
||||
FLOATING_POINT task, the state of the numeric coprocessor will
|
||||
never be saved or restored. When the first FLOATING_POINT task
|
||||
is dispatched, RTEMS does not need to save the current state of
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the numeric coprocessor.
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||||
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The following table summarizes the context switch
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times for the RTEMS_BSP benchmark platform:
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@include timetbldmv177.texi
|
||||
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||||
@tex
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||||
\global\advance \smallskipamount by 4pt
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||||
@end tex
|
||||
|
||||
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||||
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